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cpad-waltz(S5L840F) internet audio decoder for flash memory media data sheet 1 introduction S5L840F is a single chip digital audio player ic suppor ting various compressed audio format on flash memory media. S5L840F provides 2mbits of embedded nor flas h memory and 76kbytes of sram requiring no external memory. a 16bit risc processor (calmrisc16 tm ) and 24bit mac(mac2424 tm ) are provided as a cpu and dsp function. features ? supply voltage range: - supply voltage (core) : 1.8v - supply voltage (io) : 3.0v ? x-tal oscillator: 32.768 khz ? 16bit risc(calmrisc16) & 24bit mac with 4kb of instruction cache 6kb of x cache 6kb of y cache ? 2mbit nor flash & 76kb sram ? io dma ? supports smc/mmc/sd/memory stic ? lcd controller interface ? 2 channels of iis ? iic / spdif output / uart / spi ? usb1.1 ? 5 channel 10bit adc ? rtc ? gpio typical application ? mp3/wma/etc player ordering information device package operating temperature S5L840F 128-tqfp-1414 ?40 c ? +85 c
block diagram memory controller ahb to apb bridge io dm a 2mbit nor-flash calmadm 3 rtc timer clock gen gpio uart iic(m/s) spi iis out spdif out iis in sd/mmc i/ f smc i/f interrupt controller 10bit adc memory stick i/ f 76kb sram wdt 4kb rom 3 3 2 2 b b i i t t a a h h b b p p l l u u s s 3 3 2 2 b b i i t t a a p p b b lcd if usb1.1
cpad-waltz S5L840F 3 pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 S5L840F (ver 35) 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p3.1/clk_ms io6/p4.6 d0(ms)/io14/p5.6 io7/p4.7 bs(ms)/io15/p5.7 nre/p6.0 nce0/p6.1 nce1/p6.2 nce2/p6.3 cle/p6.4 ale/p6.5 nwe/p6.6 nwp/p6.7 sd1/p7.0 lrclk/p7.1 intvss4 intvdd4 sd0/p7.2 bclk/p7.3 mclk/p7.4 p10.0 p10.1 p10.2 p10.3 padvdd3 padvss3 intvss3 intvdd3 io4/p4.4 d2(sdc)/io12/p5.4 io5/p4.5 io13/p5.5 p10.6 p10.7 mosi/p1.0 miso/p1.1 spisck/p1.2 runst nreset intvdd5 scl/p1.3 sda/p1.4 nssi/p1.5 padvdd4 padvss4 clksel intvss6 intvdd6 vddpll0 vsspll0 cp0 vddpll1 vsspll1 cp1 avref avss adc0 adc1 adc2 adc3 adc4 p10.4 p10.5 intvss5 rx/p0.4 tx/p0.5 ld1 / p8.1 ld2 / p8.2 ld3 / p8.3 ld4 / p8.4 ld5 / p8.5 ld6 / p8.6 ld7 / p8.7 test2/ debug test1 test_clk tck tms tdi tdo intvss1 intvdd1 padvss1 padvdd1 exhv vcc3f nerr/ sdat/ eint4 / p1.6 sclk/ eint5 / p1.7 vddf vssf xout xin test0/ tool exhven ld0/p8.0 nrst_adm eint6/p0.6/sdwp intvss2 d1(sdc)/io8/p5.0 taout/p0.1 tcck/p0.2 eint7/p0.7/rbn padvdd2 padvss2 intvdd2 io0/p4.0 io1/p4.1 d0(sdc)/io9/p5.1 io2/p4.2 clk_mmc_sdc/p3.0 cmd(sdc)/io10/p5.2 io3/p4.3 ld_re/p9.0 ld_we/p9.1 ld_cs/p9.2 ld_reg/p9.3 ld_rst/p9.4 tack/tacap/p0.0 spdif/p0.3 d3(sdc)/io11/p5.3 eint2/p2.2 eint0/p2.0 eint1/p2.1 eint3/p2.3 dm dp vddusb vssusb
pin description pin number pin assignment i/o pin description 1 test2/debug i debug(internal f/f value dump) control 2 test1 i test mode 3 test_clk(for debug) i test clock 4 tck i jtag clock. pull-up. 5 tms i jtag mode selection. pull-up. 6 tdi i jtag input 7 td0 o jtag output 8 exhv b flash high voltage test 9 vcc3f p flash memory internal 3.3v power. 10 nerr/eint4/p1.6 b uart, gpio 11 eint5/p1.7 b uart, gpio 12 vddf p flash memory internal 1.8v power. 13 vssf p gnd for flash core 14 xout o crystal oscillator signal (~100khz) 15 xin i crystal oscillator signal (~100khz) 16 test0/tool_mode i bus/serial controller selection. pull-down 17 exhven i flash high volatge test enable. pull-down 18 ld0/p8.0 b lcd i/f 19 ntrst_adm i adm reset. pull-up. 20 padvss1 p pad power gnd 21 padvdd1 p pad power vdd 3.3v 22 intvss1 p internal logic gnd 23 intvdd1 p internal logic power vdd 1.8v 24 ld1/p8.1 b lcd i/f
cpad-waltz S5L840F 5 25 ld2/p8.2 b lcd i/f 26 ld3/p8.3 b lcd i/f 27 ld4/p8.4 b lcd i/f 28 ld5/p8.5 b lcd i/f 29 ld6/p8.6 b lcd i/f 30 ld7/p8.7 b lcd i/f 31 rx/p0.4 b int, gpio 32 tx/p0.5 b int, gpio 33 ld_re/p9.0 b lcd i/f 34 ld_we/p9.1 b lcd i/f 35 ld_cs/p9.2 b lcd i/f 36 ld_reg/p9.3 b lcd i/f 37 ld_rst/p9.4 b lcd i/f 38 tack/tacap/p0.0 b timer a, gpio 39 taout/p0.1 b timer a, gpio 40 tcck/p0.2 b timer c, gpio 41 spdif/p0.3 b spdif, gpio 42 eint6/p0.6/sdwp b int, gpio, sdc_wp 43 eint7/p0.7/rbn b int, gpio, rbn(smc) 44 padvdd2 p pad power vdd 3.3v 45 padvss2 p pad power gnd 46 intvss2 p internal logic gnd 47 intvdd2 p internal logic power vdd 1.8v 48 eint0/p2.0 b int, gpio 49 eint1/p2.1 b int, gpio 50 eint2/p2.2 b int, gpio
51 eint3/p2.3 b int, gpio 52 dm b usb transceive/receive port 53 dp b usb transceive/receive port 54 vddusb p usb power 3.3v 55 vssusb p usb ground 56 io0/p4.0 b io0 for smc /debug scan in 57 d1(sdc)/io8/p5.0 b io8 for smc, d0 for sdc 58 io1/p4.1 b io1 for smc 59 d0(sdc)/io9/p5.1 b io9 for smc, d1 for sdc 60 io2/p4.2 b io2 for smc 61 clk_mmc_sdc/p3.0 b clk for mmc/sdc 62 cmd(sdc)/io10/p5.2 b io10 for smc, cmd/resp for sdc 63 io3/p4.3 b io3 for smc 64 d3(sdc)/io11/p5.3 b io11 for smc, d3 for sdc 65 padvdd3 p pad power vdd 3.3v 66 padvss3 p pad power gnd 67 intvss3 p internal logic gnd 68 intvdd3 p internal logic power vdd 1.8v 69 io4/p4.4 b io4 for smc 70 d2(sdc)/io12/p5.4 b io12 for smc, d2 for sdc 71 io5/p4.5 b io5 for smc 72 io13/p5.5 b io13 for smc 73 p3.1/clk_ms b gpio, clk for ms 74 io6/p4.6 b io6 for smc 75 d0(ms)/io14/p5.6 b io14 for smc, d0 for ms 76 io7/p4.7 b io7 for smc
cpad-waltz S5L840F 7 77 bs(ms)/io15/p5.7 b io15 for smc, bs for ms 78 nre/p6.0 b smc control 79 nce0/p6.1 b smc control 80 nce1/p6.2 b smc control 81 nce2/p6.3 b smc control 82 cle/p6.4 b smc control 83 ale/p6.5 b smc control 84 nwe/p6.6 b smc control /debug scan out 85 nwp/p6.7 b smc control 86 sd1/p7.0 b serial data in for iis 87 lrclk/p7.1 b left-right clock for iis 88 intvss4 p internal logic gnd 89 intvdd4 p internal logic power vdd 1.8v 90 sd0/p7.2 b serial data out for iis 91 bclk/p7.3 b bit clock for iis 92 mclk/p7.4 b over-sampling clock for iis 93 p10.0 b gpio 94 p10.1 b gpio 95 p10.2 b gpio 96 p10.3 b gpio 97 avref p adc vref,avdd33a1,avdd33a2 ?? . 3.3v power 98 avss p adc analog gnd. avss33a1,avbb33a1,avss33a2 99 adc0 i adc 100 adc1 i adc 101 adc2 i adc 102 adc3 i adc
103 adc4 i adc 104 p10.4 b gpio 105 p10.5 b gpio 106 p10.6 b gpio 107 p10.7 b gpio 108 mosi/p1.0/tclk0 b spi, gpio, tclk0(not open) 109 miso/p1.1/tclk1 b spi, gpio, tclk1(not open) 110 spisck/p1.2 b spi, gpio 111 runst b jtag runid / test mode select 112 nreset i system reset. pull-up. 113 intvss5 p internal logic gnd 114 intvdd5 p internal logic power vdd 1.8v 115 scl/p1.3 b iic, gpio 116 sda/p1.4 b iic, gpio 117 nssi/p1.5 b spi, iic, uart 118 padvdd4 p pad power vdd 3.3v 119 padvss4 p pad power gnd 120 clksel i clock selection signal. pull-up. 121 intvss6 p internal logic gnd 122 intvdd6 p internal logic power vdd 1.8v 123 vddpll0 p pll power supply vdd 1.8v 124 vsspll0 p pll gnd 125 cp0 o low pass filter circuit for pll0 126 vddpll1 p pll power supply vdd 1.8v 127 vsspll1 p pll gnd 128 cp1 o low pass filter circuit for pll1
cpad-waltz S5L840F 9 absolute maximum ratings characteristic symbol value unit supply voltage vdd 3.8 v input voltage vin 6.5 v storage temperature range tstg -65?150 c electrical characteristics recommended operating conditions characteristic symbol value unit supply voltage vdd 1.65~1.95(core), 2.7~3.3(io) v operating temperature range topr -40?85 c dc characteristics (ta = 25 c, vdd(io) = 3.3v, unle ss otherwise specified) symbol characteristic test conditions min typ max unit vih high level input voltage ? 2.0 ? ? v vil low level input voltage ? ? ? 0.8 v vt switching threshold 1.4 v vt+ schmitt trigger, positive ?going threshold cmos 2.0 v vt- schmitt trigger, negative-going threshold cmos 0.8 v voh high level output voltage ioh = -2ma 2.4 ? ? v vol low level output voltage iol = 2ma ? ? 0.4 v ioz tri-state output leakage current vout = vss or gnd -10 ? 10 a notes:
package dimensions
low-power & high-performance risc core calmrisc16 technical reference manual mcu team lsi division system lsi business samsung electronics co.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 2 - mcu team lsi division system lsi business april 2000 1. introduction 1.1 feature the main features of calmrisc 16, a 16-bit embedded risc mcu core, are high performance, low power consumption, and efficient coprocessor interface. it can operate up to 100mhz, and consumes 100 a/mhz @3.3v. when operating with mac2424, a 24-bit fixed point dsp coprocessor, calmrisc16 can operate up to 80mhz. through effici ent coprocessor interface, calmrisc16 provides a powerful and flexible mcu+dsp solution. the following gives brief summary of main features of calmrisc16. ? h/w feature - power consumption : 100 a per mhz @3.3v, 0.35 process - maximum frequency : 100mhz @3.3v - 0.78 mm 2 die size ? architecture - harvard risc architecture - 5-stage pipeline ? registers - sixteen 16-bit general registers - eight 6-bit extension registers - 22-bit program counter (pc) - 16-bit status register (sr) - seven saved registers for interrupts. ? instruction set - 16-bit instruction width for 1-word instructions - 32-bit instruction width for 2-word instructions - load/store instruction architecture - delayed branch support - c-language/os support - bit operation for i/o process ? instruction execution time - one instruction/cycle fo r basic instructions ? address space - 4m byte for program memory - 4m byte for data memory
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 3 - mcu team lsi division system lsi business april 2000 1.2. registers in calmrisc16 there are sixteen 16-bit general registers, eight 6-bit extension registers, a 16-bit status register(sr), a program counter (pc), and seven saved registers. general registers & extension registers the following figure shows the st ructure of the general registers and the extension registers. the general registers (from r0 to r15) can be either a source register or a destination register for almost all alu operations, and can be used as an inde x register for memory load/store instructions (e.g., ldw r3, @[a8+r2]). the 6-bit extension registers (from e8 to e15) are used to form a 22-bit address register (from a8 to a15) by concatenating with a general register (from r8 to r15). the address registers are used to generate 22-bit program and data addresses. special registers the special registers consist of 16-bit sr (status register), 22-bit pc (program counter), and saved registers for irq(interrupt), fiq(fast interrupt), and swi(software interrupt). when irq interrupt occurs, the most significant 6 bits of the return address are saved in spch_irq, the least significant 16 bits of r0 r1 r7 r8 r9 r14 r15 address registers registers for byte stack pointer link register e15 e14 e9 e8 pc sr spc_fiq spc_irq ssr_fiq ssr_irq ssr_swi register structure in calmrisc16
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 4 - mcu team lsi division system lsi business april 2000 the return address are saved in spcl_irq, and the status register is saved in ssr_irq. when fiq interrupt occurs, the most significant 6 bits of th e return address are save d in spch_fiq, the least significant 16 bits of the return address are saved in spcl_fiq, and the status register is saved in ssr_fiq. when a swi instruction is executed, the return address is saved in a14 register (e14 concatenated with r14), and the status register is saved in ssr_swi. the least significant bit of pc, spcl_irq and spcl_fiq is read only and its value is always 0. the 16-bit register sr has the following format. 15 8 7 0 t - - - - - - - - pm z1 z0 v te ie fe ? fe : fiq enable bit, fiq is enabled when fe is set. ? ie : irq enable bit, irq is enabled when ie is set. ? te : trq enable bit, trace is enabled when te is set. ? v : overflow flag, set/clear accordingly wh en arithmetic instructions are executed. ? z0 : zero flag of r6, set when r6 equals zero and used as the branch condition when bnzd instruction with r6 is executed. ? z1 : zero flag of r7, set when r7 equals zero and used as the branch condition when bnzd instruction with r7 is executed. ? pm : privilege mode bit. pm = 1 for privilege mode and pm = 0 for user mode ? t : true flag, set/clear as a result of an alu operation. fe, ie, te, and pm bits can be modified only when pm = 1 (privilege mode). the only way to change from user mode to privilege mode is via interrupts including swi instructions. the reserved bit of sr (from bit 7 to bit 14) can be used for other purposes without any notice. hence programmers should not depend on the value of the reserved bits in their programming. the reserved b its are read as 0 value. 1.3. pipeline structure calmrisc16 has a 5-stage pipeline architecture. it take s 5 cycles for an instruc tion to do its operation. in a pipeline architecture, instructions are executed overlapped, hence the throughput is one instruction per cycle. due to data dependency, control dependen cy, and 2 word instructions, the throughput is about 1.2 on the average. the following diagra m depicts the 5-stage pipeline structure. if id ex mem wb in the first stage, which is called if (instruction fe tch) stage, an instruction is fetched from program
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 5 - mcu team lsi division system lsi business april 2000 memory. in the second stage, which is called id (inst ruction decoding) stage, th e fetched instruction is decoded, and the appropriate operands, if any, for alu operation are prepared. in the case of branch or jump instructions, the target address is calculated in id stage. in the third stage, which is called ex (execution) stage, alu operation and data address calcu lation are executed. in the fourth stage, which is called mem (memory) stage, data transfer from/to data memory or program memory is executed. in the fifth stage, which is called wb (write back) stage, a write-back to register file can be executed. the following figure shows an example of pipeline prog ress when 3 consecutive inst ructions are executed. i1 : add r0, 3 if id ex mem wb i2 : add r1, r0 if id ex mem wb i3 : ld r2, r0 if id ex mem wb in the above example, the instructio n i2 needs the result of the instruction i1 before i1 completes. to resolve this problem, the ex stage result of i1 is forwarded to id stage of i2. similar forwarding mechanism occurs from mem stag e of i1 to id stage of i3. the pipeline cannot progress (called a pipeline stall) due to a data dependency, a control dependency, or a resource conflict. when a source operand of an alu instruction is from a register, which is loaded from memory in the previous instruction, 1 cycle of pipeline stall occurs (called load stall). such load stalls can be avoided by smart reordering of the instruction sequences. calmrisc16 has 2 classes of branch instructions, those with a delay slot and without a delay slot. non-delay slot branch instructions incurs a 1 cycle pipeline stall if the branch is taken, due to a control depend ency. for branch instructions with a delay slot, no cycle waste is incurred if the delay slot is filled with a useful instruction (or non nop instruction). pipeline stalls due to resource conflicts occurs when two different instructions access at the same cycle the same resource such as the data memory and the program memory. ldc (data load from program memory) instruction causes a resource conflict on the program memory. bit operations such as bitr and bits (read-modify-write instructions) caus e a resource conflict on the data memory. 1.4 interrupts in calmrisc16, there are five interrupts: reset, fiq, irq, trq, swi. the reset, fiq, and irq interrupts correspond to external requests. trq an d swi interrupts are initiated by an instruction (therefore, in a deterministic way). the follo wing table shows a summary of interrupts. name priority address description reset 1 000000h hardware reset fiq 3 000002h fast interrupt request
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 6 - mcu team lsi division system lsi business april 2000 irq 5 000004h interrupt request trq 2 000006h trace request swi 4 000008h ~ 0000feh software interrupt when nres (an input pin calmrisc16 core) signal is released (transition from 0 to 1), ?jmp addr:22? is automatically executed by calmrisc16. among the 22-bit address addr:22, the most significant 6 bits are forced to 0, and the least signifi cant 16 bits are the contents of 000000h (i.e., reset vector address) of the program memory. in other words, ?jmp {6?h00 1 , pm[000000h]}? instruction is forced to the pipeline. the initial value of pm bit is 1 (that is, in privilege mode) and the initial values of other bits in sr register are 0. all other registers are not initialized (i.e., unknown). when nfiq (an input pin calmrisc16 core) signal is active (transition from 1 to 0), ?jmp addr:22? instruction is automatically executed by calmrisc16. the address of fiq interrupt service routine is in 000002h (i.e., fiq vector address) of the program memory (i.e., ?jmp {6?h00, pm[000002h]}?). the return address is saved in {spch_fiq, spcl_fiq} register pair, and the sr value is saved in ssr_fiq register. pm bit is set. fe, ie, and te bits are cl eared. when ret_fiq instruction is executed, sr value is restored from ssr_fiq, and the return address is restored into pc from {spch_fiq, spcl_fiq}. when nirq signal (an input pin calmrisc16 core) is active (transition from 1 to 0), ?jmp {6?h00, pm[000004h]}? instruction is forced to the instru ction pipeline. the return address is saved in {spch_irq, spcl_irq} register pair, and the sr value is saved in ssr_irq register. pm bit is set. ie and te bits are cleared. when ret_ irq instruction is executed, sr value is restored from ssr_irq, and return address is restored to pc from {spch_irq, spcl_irq}. when te bit is set, trq interrupt happens and ?jmp {6?h00, pm[000006h]}? instruction is executed right after each instruction is executed. trq inte rrupt uses the saved registers of irq(that is, {spch_irq, spcl_irq} register pa ir and ssr_irq) to save the return address and sr, respectively. pm bit is set. ie, te bits are cleared. when ?swi imm:6 2 ? instruction is executed, the return address is saved in the register a14, and the value of sr is saved in ssr_swi. then the program sequence jumps to the ad dress (imm:6 * 4). pm bit is set. ie and te bits are cleared. ?swi 0? and ?swi 1? are prohibited because the addresses are reserved for other interrupts. when ret_swi instruction is executed, sr is restored from ssr_swi, and the return address is restored to pc from a14. 1.5 memory formats 1 6?h00 is defined as 00 (or zero) in 6 bits 2 imm:6 is defined as 6-bit immediate number
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 7 - mcu team lsi division system lsi business april 2000 calmrisc16 adopts a big endian memory format . in a big endian memory format, the most significant byte of word data is stored at an even addr ess, and the least significant byte is stored at an odd address. for example let us assume that the word data ?1234h? is stored at the address 100h. then the higher byte ?12h? is stored at th e address 100h, and the lower byte ?34h? is stored at the address 101h. when the 22-bit data ?123456h? is stored at the addr ess 100h by ?ldw @an, ai? instruction, ?00h? is at the address 100h, ?12h? is at the ad dress 101h, ?34h? is at the address 102h, and ?56h? is at the address 103h. 1.6 signal description name direction description pa[20:0] o program memory address, equivalent to pc[21:1] pd[15:0] i program data npmcs o program memory chip selection nldc o data load from program memory indicator da[21:0] o data memory address da[4:0] is shared with sys and cld instructions di[15:0] i input from data memory, input from coprocessor for cld instruction. do[15:0] o output to data memory, output to coprocessor for cld instruction. ndmcsh o chip selection for higher byte data memory ndmcsl o chip selection for lower byte data memory dmwr o data memory write, 1 means transfer from core to memory ndme o data bus enable signal. nres i hardware reset nfiq i fast interrupt request nirq i interrupt request nexpack o exception acknowledge nwait i wait signal, core is stopped when active. nsysid o sys instruction indicator mclk i main clock input eclk o early clock output iclk o clock output ncopid o coprocessor instruction indicator ncldid o coprocessor load instruction indicator cldwr o write to coprocessor indicator
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 8 - mcu team lsi division system lsi business april 2000 copir[12:0] o instruction to coprocessor, 13-bit immediate field in cop instruction. ec[3:0] i external conditions from coprocessor or peripherals. nbrk o software break indicator nbkack o break acknowledge bkmode[2:0] o break mode, indicates core state when core breaks. bkreq i break request ngidis i global interrupt disable, wh en active, all interrupt is disabled. pdgrant i indicates program memory access is permitted. pdwait i indicates cu rrent program memory access is not complete. dbgrant i indicates data memory access is permitted. dbwait i indicates current data memory access is not complete. dbreq o signal asking for data bus permission. pmode o privilege mode indicator cgrant o indicates that coprocessor may use data bus. cstall i coprocessor indicates that coprocessor pipeline stall occurs. cmw i coprocessor indicates that copr ocessor instruction is multiple word. nseq o indicates that the next program address is sequential. nincpc i if it is 1, pc value is not incremented when sequential execution. cclk o clock output to coprocessor 2. instructions 2.1. alu instructions in operations between a 16-bit general register an d an immediate value, th e immediate value is zero- extended to 16-bit. the following figure sh ows an example of 7-b it immediate numbers. 7-bits immediate 7-bits immediate '0' imm:7 15 7 60 in operations between a 22-bit register and an imme diate value, the immediate value is zero-extended to
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 9 - mcu team lsi division system lsi business april 2000 22-bit. in operations between a 22-bit register and a 16 -bit register, the 16-bit register is zero-extended to 22-bit. the overflow flag in a 16-bit arithmetic ope ration is saved to v flag in sr register. alu instructions are classified into 3 classes as follows. ? aluop register, immediate ? aluop register, register ? aluop register aluop register, immediate add/adc/sub/sbc/and/or/xor/tst/cmp/cmpu rn, #imm:16 the instructions perform an alu operation of which source operands are a 16-bit general register rn and a 16-bit immediate value. in the in structions tst/cmp/cmpu, only t fl ag is updated accordingly as the result. in the instructions add/adc/sub/sbc, the value of t flag is the carry flag of the operations, and the value of v flag indicates whether overflow or underflow occurs. in the instructions and/or/xor/tst, the value of t fl ag indicates whether the result is zero (t=1). ?cmp {gt|ge|eq}, rn, #imm:16 3 ? instructions are for signed comparison opera tions (gt for greater than, ge for greater than or equal to and eq for equal to), and ?cmpu {gt|ge}, rn, #imm:16? instructions are for unsigned comparison operations. add/sub an, #imm:16 the immediate value is zero-extended to 22-bit value. no flag update occurs. add/sub rn, #imm:7 the immediate value is zero-extended to 16-bit value. t flag is updated to the carry of the operation. v flag is updated. and/or/xor/tst r0, #imm:8 the immediate value is zero-extended to 16-bit value. t flag indicates whether the lower 8-bit of the logical operation result is zero. cmp eq, rn, #imm:8 the immediate value is zero-extended to 16-bit value. rn is restricted to r0 to r7. t flag is updated as the result of the instruction. 3 imm:16 is defined as a 16-bit immediate number
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 10 - mcu team lsi division system lsi business april 2000 cmp ge, rn, #imm:6 the immediate value is zero-extended to 16-bit value. the instruction is for signed compare. t flag is updated as the result of the instruction. add/sub an, #imm:5 the immediate value is zero-extended to 22-bit value. no flag is updated. aluop register, register add/sub/adc/sbc/and/or/xor/tst/cmp/cmpu rn, ri the instructions perform an alu operation of which source operands are a pair of 16-bit general registers. in the instructions tst/cmp/cmpu, only t flag is updated as the result. in the instructions add/adc/sub/sbc, the value of t flag is the carry of the operations, and the value of v flag indicates whether overflow or underflow occurs. in the instructions and/or/xor/tst, the value of t flag indicates whether the result is zero. ?cmp {gt|ge|e q}, rn, ri? instructions are for signed comparison, and ?cmpu {gt|ge}, rn, ri? instruc tions are for unsi gned comparison. add/sub an, ri 16-bit general register ri is zero-extended to 22-bit value. the result is saved in the 22-bit register an. no flag update occurs. cmp eq, an, ai the instruction compares two 22-bit registers. mul {ss|su|us|uu}, rn, ri the general registers rn and ri can be one of r0 to r7. the instruction multiplies the lower byte of rn and the lower byte of ri, and the 16-bit result is saved in rn. the optional field, ss, su, us, and uu, indicates whether the source operands are signed value or unsigned value. the first letter of the two letter qualifiers corresponds to rn, and the second correspond s to ri. for example, in the instruction ?mul su, r0, r1?, the 8-bit signed value in the lower byte of r0 and the 8-bit unsigned value in the lower byte of r1 are multiplied, and the 16-bit result is saved in r0. rr/rl/rrc/sr/sra/slb/srb/dt/inc c/decc/com/com2/comc/ext rn for ?dt rn?(decrement and test) and ?com rn?(comp lement) instructions, t flag indicates whether the result is zero. in the instruction of ?ext rn?(sign extend), no flag update occurs. in all other instructions, carry-out of the operation is transferred to t flag. in the instruction of dt, incc, and decc,
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 11 - mcu team lsi division system lsi business april 2000 v flag indicates whether overflow or underflow occurs. 2.2. load instructions ? load instructions? move data from register/memory/immediate to register/memory. when the destination is a memory location, only general regist ers and extension registers can be the source. we can classify ?load instructions? into the following 4 classes. ? ld register, register ? ld register, immediate ? ld data memory, register / ld register, data memory ? ld register, program memory ld register, register ld rn, ri / ld an, ai the instructions move 16-bit or 22-bit data from the so urce register to the des tination register. when the destination register is r6/r7, the zero flag z0/z1 is updated. in all other cases, no flag update occurs. ld rn, ei / ld en, ri in the instruction ?ld rn, ei?, the 6-bit data in ei is zero-extended to 16-bit data, and then transferred to rn. when the destination register is r6/r7, the zero fl ag z0/z1 is updated. in the instruction ?ld en, ri?, least significant 6 bits of ri ar e transferred to en. rn/ri is one of the registers from r0 to r7. ld r0, spr / ld spr, r0 spr : sr, spcl_fiq, spch_fiq, ssr_fiq, spcl_irq, spch_irq, ssr_irq, ssr_swi the instructions transfer data betw een spr (special purpose registers) and r0. no flag update occurs except the case that the destination register is sr. ld an, pc the instruction moves the value of (pc+4) to an. ld register, data memory / ld data memory, register ldw rn, @[sp+edisp:9] / ldw @[sp+edisp:9], rn the instructions transfer 16-bit da ta between a general register rn an d the memory location at the address of (sp+edisp:9). note sp is another name of a15. edisp:9 is an ev en positive displacement from 0 to 510.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 12 - mcu team lsi division system lsi business april 2000 edisp:9 is encoded into an 8-bit displacement value in the instruction map because the lsb is always 0. when the address is calculated, the 8- bit displacement field is shifted to the left by one bit, and then the result is added to the value of sp. even if the addr ess might be specified as odd in assembly mnemonic, the lsb of the address should be trun cated to zero for word alignment. ldw rn, @[ai+edisp:5] / ldw @[ai+edisp:5], rn the instructions transfer 16-bit da ta between a general register rn an d the memory location at the address of (ai+edisp:5). edisp:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement value in the instructio n map because the lsb is always 0. when the address is calculated, the 4-bit displacement field is shifted to the left by one bit, and then the result is added to the value of ai. even if the address might be specified as odd in assembly mnemonic, the lsb of the address should be truncated to zero fo r word alignment. ldw rn, @[ai+disp:16] / ldw @[ai+disp:16], rn the instructions transfer 16-bit da ta between a general register rn an d the memory location at the address of (ai+disp:16). disp:16 is an positive displacement from 0 to ffffh. if the address is odd, the lsb of the address is set to zero for word alignment. ldw rn, @[ai+rj] / ldw @[ai+rj], rn the instructions transfer 16-bit da ta between a general register rn an d the memory location at the address of (ai+rj). the value of rj is zero-extended to 22-bit value. if the address is odd, the lsb of the address is set to zero for word alignment. ldw an, @[ai+edisp:5] / ldw @[ai+edisp:5], an the instructions transfer 22-bit data between an ad dress register an and th e memory location at the address of (ai+edisp:5). edis p:5 is an even positive displacement from 0 to 30. edisp:5 is encoded into an 4-bit displacement value in the instruction map b ecause the lsb is always 0. when the address is calculated, the 4-bit displacement field is shifted to the left by one bit, and then the result is added to the value of ai. even if the address might be specified as odd in assembly mnemoni c, the lsb of the address should be truncated to ze ro for word alignment. ldw an, @[ai+disp:16] / ldw @[ai+disp:16], an the instructions transfer 22-bit data between an ad dress register an and th e memory location at the address of (ai+disp:16). di sp:16 is an positive displacement from 0 to ffffh. if the ad dress is odd, the lsb of the address is set to zero for word alignment. ldw an, @[ai+rj] / ldw @[ai+rj], an
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 13 - mcu team lsi division system lsi business april 2000 the instructions transfer 22-bit data between an ad dress register an and th e memory location at the address of (ai+rj). the value of rj is zero-extended to 22-bit value. if the address is odd, the lsb of the address is set to zero for word alignment. push rn/push rn, rm/p ush an/ push an, am the instruction ?push rn? transfers 16-bit data from the register rn to the memory location at the address of sp, and then increments the value of sp by 2. the register rn should not be r15. the operation of ?push r15? is undefined. the instruction ?push rn, rm? pushes rn and then rm. the registers rn and rm should not be the same. the registers rn and rm should not be r15. the instruction ?push an? pushes rn and then en. when the extension register en is pushed, the value of en is zero- extended to 16-bit data. the register an should not be a15. the instruction ?push an, am? pushes an and then am. the registers an and am should not be the same pop rn/pop rn, rm/pop an/ pop an, am the instruction ?pop rn? decrements the value of sp by 2, and then tran sfers 16-bit data to the register rn from the memory location at the address of sp. the register rn should not be r15. the operation of ?pop r15? is undefined. the instruction ?pop rn, rm? pops rn and then rm. the registers rn and rm should not be the same. the registers rn and rm should not be r15. the instruction ?pop an? pops en and then rn. when the extension register en is popped, the least significant 6 bits are transferred to en. the register an should not be a15. the instructio n ?pop an, am? pops an and then am. the registers an and am should not be the same ldb rn, @[ai+disp:4] / ldb @[ai+disp:4], rn the instructions transfer 8-bit da ta between the general register rn and the memory location at the address of (ai+disp:4). disp:4 is a positive displacement from 0 to 15. th e general register rn is one r0 to r7. in the instruction ?ldb rn, @[ai+disp:4]?, the 8-bit data is zero-extended to 16-bit data, and then written into rn. in the instruction ?ldb @[ai+disp:8], rn?, the least significant byte of rn is transferred to the memory. ldb rn, @[ai+disp:16] / ldb @[ai+disp:16], rn the instructions transfer 8-bit da ta between the general register rn and the memory location at the address of (ai+disp:16). disp:16 is a positive displacement from 0 to ffffh. the general register rn is one of r0 to r7. in the instruction ?ldb rn, @[ ai+disp:16]?, the 8-bit data is zero-extended to 16- bit data, and then written into rn. in the instruction ?ldb @[ai+disp:16], rn?, the least significant byte of rn is transfe rred to the memory. ldb r0, @[a8+disp:8] / ldb @[a8+disp:8], rn
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 14 - mcu team lsi division system lsi business april 2000 the instructions transfer 8-bit da ta between the general register r0 and the memory location at the address of (a8+disp:8). disp:8 is a positive displacement from 0 to 25 5. in the instruction ?ldb r0, @[a8+disp:8]?, the 8-bit data is zero-extended to 16- bit data, and then written into r0. in the instruction ?ldb @[a8+disp:8], r0?, the least significant byte of r0 is transferred to the memory. ldb rn, @[ai+rj] / ldb @[ai+rj], rn the instructions transfer 8-bit da ta between the general register rn and the memory location at the address of (ai+rj). the value of rj is zero-extended to 22-bit value. the general register rn is one of the 8 registers from r0 to r7. in the instruction ?ldb rn , @[ai+rj]?, the 8-bit data is zero-extended to 16- bit data, and then written into r0. in the instruction ?ldb @[ai+rj], rn?, the least significant byte of rn is transferred to the memory. ld register, program memory ldc rn, @ai the instruction transfers 16-bit data to rn from program memory at the address of ai. ld register, # immediate ld rn, #imm:8 / ld rn, #imm:16 / ld an, #imm:22 the instructions move an immediate data to a register. in the instruction ?ld rn, #imm:8?, the immediate value is zero-extended to 16-bit value. 2.3. branch instructions calmrisc16 has 2 classes of branch instru ctions: with a delay slot and without a delay slot. if a delay slot is filled with a useful instruction (or an instruction which is not nop), then the performance degradation due to the control dependency can be minimized. however, if the delay slot ca nnot be used, then it should be nop instruction, which can increase the program code si ze. in this case, the corresponding branch in struction without a delay slot can be used to avoid using nop. some instructions are not permitted to be in the de lay slot. the prohibited instructions are as follows. - all 2-word instructions - all branch and jump instructions incl uding swi, retd, ret_swi, ret_irq, ret - break instructions when a prohibited instruction is in the delay slot, the operation of calm risc16 is undefined or unpredictable. bsrd eoffset:13
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 15 - mcu team lsi division system lsi business april 2000 in the instruction, called branch subroutine with a delay slot, the value (pc + 4) is saved into a14 register, the instruction in the delay slot is executed, and then the program sequence is moved to (pc + 2 + eoffset:13), where pc is the ad dress of the instruction ?bsrd eoffset:13?. the immediate value eoffset:13 is sign-extended to 22-bit and then added to (pc+2). in general, the 13-bit offset field appears as a label in assembly programs. if the instruction in the delay slot reads the value of a14, the value (pc+4) is read. the even offset eoffset:13 is encoded to 12bit signed offset in instruction map by dropping the least significant bit. bra/brad/brt/brtd/brf/brfd eoffset:11 in the branch instructions, the targ et address is (pc + 2 + eoffset:11) . the immediate value eoffset:11 is sign-extended to 22-bit and then added to (pc+2). the ?d? in the mnemonic stands for a delay slot. in general, the 11-bit offset field appears as a labe l in assembly programs. bra and brad instructions always branch to the target address. brt and brtd inst ructions branch to the target address if t flag is set. brf and brfd instructions branch to the ta rget address if t flag is cleared. brad/brtd/brfd instructions are delay slot branch instructions, therefor e the instruction in the delay slot is executed before the branch to the target address or the branch decision is made. the even offset eoffset:11 is encoded to 10-bit signed offset in instruction map by dropping the least significant bit. bra/brad ec:2, eoffset:8 in the branch instructions, the target address is (p c + 2 + eoffset:8). the imme diate value eoffset:8 is sign-extended to 22-bit and then added to (pc+2). the ec:2 field indicates one of the 4 external conditions from ec0 to ec3 (input pin signals to calmrisc16). when the external condition corresponding to ec:2 is set, the program branches to the target address. brad has a delay slot. the even offset eoffset:8 is encoded to 7-bit signed offs et in instruction map by dr opping the least significant bit. bnzd r6/r7, eoffset:8 in the branch instruction, the target address is (pc + 2 + eoffset:8). the immediate value eoffset:8 is sign- extended to 22-bit and then added to (pc+2). ?bnzd r6, eoffset:8? instruction branches to the target address if z0 flag is cleared. ?bnz d r7, eoffset:8? instruction branches if z1 flag is cleared. before the branch operation, the instruction d ecrements r6/r7, updates z0/z1 flag according to the decrement result, and then executes the instruction in the delay slot. th e instruction is used to manage loop counter with just one cycle overhead. in the end of the loop, the value of r6/r7 is ?1. when the instruction in the delay slot read the z0/z1 flag, the result after the decr ement is read. the even offset eoffset:8 is encoded to 7-bit signed offset in instruction map by dropping the least significant bit. jmp/jpt/jpf/jsr addr:22
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 16 - mcu team lsi division system lsi business april 2000 the target address of the instructions is addr:22. jmp always branches to the target address. jpt branches to the target address if the t flag is set. jpf branches if the t flag is cleared. jsr always branches to the target address with saving the return address (pc+4) into a14. the instructions are 2 word instructions. jmp/jpt/jpf/jsr ai the target address of the instructions is the value of ai. jmp always br anches to the target address. jpt branches to the target address if the t flag is set. jpf branches if the t flag is cleared. jsr always branches to the target address with savi ng the return address (pc+2) into a14. swi #imm:6/ ret_swi/ret_irq/ret_fiq refer to the section for interrupts. retd the instruction branches to the address in a14 after the execution of the instruction in the delay slot. when there is no useful instruction adequate to the delay slot, ?jmp a14? can be used instead of ?retd?. 2.4. bit operation the bit operations manipulate a bit in sr register or in a memory location. bitr/bits/bitc/bitt @[a8+r1], #imm:3 the source as well as the destination is the 8-bit data in the data memory at the address (a8 + r1). the #imm:3 field chooses a bit position among the 8 bits. bitr resets the bit #imm:3 of the source, and then writes the result to the destination, the same memory location. bits sets the bit #imm:3 of the source, and then writes the result to the destination. bitc complements the bit #imm:3 of the source, and then writes the result to the destination. bitt does not write any data to the destination. t flag indicates whether the bit #imm:3 of the source is zero. in other words, when the bit #imm:3 of the source is zero, t flag is set. bitr and bits can be used to implement a semaphore mechanism or lock acquisition/release. clrsr/setsr/tstsr bit bit : fe, ie, te, z0, z1, v, pm clrsr instruction clears the correspon ding bit of sr. setsr instruction sets the corresponding bit of sr. tstsr tests whether the corresponding bit is zero, and stores the result in t flag. for example, when ie flag is zero, ?tstsr ie? instruction sets the t fl ag. we can clear the t flag by the instruction ?cmp gt, r0, r0?. we can set the t flag by the instruction ?cmp eq, r0, r0?.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 17 - mcu team lsi division system lsi business april 2000 2.5. miscellaneous instructions sys #imm:5 the instruction activates the output port nsysid. th e #imm:5 is transferred to outside on da[4:0]. the most significant 17 bits remain unchanged. the instruction is for system command to outside such as power down modes. cop #imm:13 the instruction activates th e output port ncopid. the #imm:13 is tran sferred to outside on copir[12:0]. the instruction is used to transfer instruction to coprocessor. the #imm:13 may be from 200h to 1fffh. cld rn, #imm:5 / cld #imm:5, rn the instruction activates th e output port ncopid, ncldid, and cldw r. the least significant 13 bits of the instruction is transferred to outside on copir[ 12:0]. the #imm:5 is transferred to outside on da[4:0]. the instructions move 16-bit data between rn and a coprocessor register implied by the #imm:5 field. cldwr signal indicates whether the data movement is from calmrisc16 to coprocessor. the register rn is one 8 registers from r0 to r7. nop no operation. break the software break instruction activates nbrk signal, and holds pa for one cycle. it?s for debugging operation. 3. calmrisc16 instruction map 15 8 7 0 add rn, #imm:7 0 0 0 0 rn 0 imm:7 sub rn, #imm:7 0 0 0 0 rn 1 imm:7 ld rn, #imm:8 0 0 0 1 rn imm:8 ldw rn, @[sp + edisp:9] 0 0 1 0 rn edisp:9 ldw @[sp + edisp:9], ri 0 0 1 1 ri edisp:9 ldw rn, @[ai + edisp:5] 0 1 0 0 rn 0 ai edisp:5 ldw rn, @[ai + rj] 0 1 0 0 rn 1 ai rj ldw @[an + edisp:5], ri 0 1 0 1 ri 0 an edisp:5
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 18 - mcu team lsi division system lsi business april 2000 ldw @[an + rm], ri 0 1 0 1 ri 1 an rm ldb dn, @[ai + disp:4] 0 1100 dn 0 ai disp:4 ldb dn, @[ai + rj] 0 1100 dn 1 ai rj ldw an, @[ai + disp:4] 0 1101 an 0 ai disp:4 ldw an, @[ai + rj] 0 1101 an 1 ai rj ldb @[an + disp:4], di 0 1110 di 0 an disp:4 ldb @[an + rm], di 0 1110 di 1 an rm ldw @[an + disp:4], ai 0 1111 ai 0 an disp:4 ldw @[an + rm], ai 0 1111 ai 1 an rm add rn, ri 1 0 0 0 rn 0 0 0 0 ri sub rn, ri 1 0 0 0 rn 0 0 0 1 ri adc rn, ri 1 0 0 0 rn 0 0 1 0 ri sbc rn, ri 1 0 0 0 rn 0 0 1 1 ri and rn, ri 1 0 0 0 rn 0 1 0 0 ri or rn, ri 1 0 0 0 rn 0 1 0 1 ri xor rn, ri 1 0 0 0 rn 0 1 1 0 ri tst rn, ri 1 0 0 0 rn 0 1 1 1 ri cmp ge, rn, ri 1 0 0 0 rn 1 0 0 0 ri cmp gt, rn, ri 1 0 0 0 rn 1 0 0 1 ri cmpu ge, rn, ri 1 0 0 0 rn 1 0 1 0 ri cmpu gt, rn, ri 1 0 0 0 rn 1 0 1 1 ri cmp eq, rn, ri 1 0 0 0 rn 1 1 0 0 ri ld rn, ri 1 0 0 0 rn 1 1 0 1 ri rr rn 1 00000001110 rn rl rn 1 00000011110 rn rrc rn 1 00000101110 rn srb rn 1 00000111110 rn sr rn 1 00001001110 rn sra rn 1 00001011110 rn jpf ai 1 00001101110 0 ai jpt ai 1 00001101110 1 ai jmp ai 1 00001111110 0 ai jsr ai 1 00001111110 1 ai slb rn 1 00010001110 rn dt rn 1 00010011110 rn
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 19 - mcu team lsi division system lsi business april 2000 incc rn 1 00010101110 rn decc rn 1 00010111110 rn com rn 1 00011001110 rn com2 rn 1 00011011110 rn comc rn 1 00011101110 rn ext rn 1 00011111110 rn add rn, #imm:16 1 00000001111 rn add an, #imm:16 1 00000011111 0 an sub an, #imm:16 1 00000011111 1 an adc rn, #imm:16 1 00000101111 rn sbc rn, #imm:16 1 00000111111 rn and rn, #imm:16 1 00001001111 rn or rn, #imm:16 1 00001011111 rn xor rn, #imm:16 1 00001101111 rn tst rn, #imm:16 1 00001111111 rn cmp ge, rn, #imm:16 1 00010001111 rn cmp gt, rn, #imm:16 1 00010011111 rn cmpu ge, rn, #imm:16 1 00010101111 rn cmpu gt, rn, #imm:16 1 00010111111 rn cmp eq, rn, #imm:16 1 00011001111 rn ld rn, #imm:16 1 00011011111 rn reserved 1 000111 1111 cmp eq, dn, #imm:8 1 0010 dn imm:8 and r0, #imm:8 1 0011000 imm:8 or r0, #imm:8 1 0011001 imm:8 xor r0, #imm:8 1 0011010 imm:8 tst r0, #imm:8 1 0011011 imm:8 ldb r0, @[a8+ disp:8] 1 0011100 disp:8 ldb @[a8+ disp:8],r0 1 0011101 disp:8 bitr @[a8+r1], bs:3 1 00111100000 0 bs:3 bits @[a8+r1], bs:3 1 00111100000 1 bs:3 bitc @[a8+r1], bs:3 1 00111100001 0 bs:3 bitt @[a8+r1], bs:3 1 00111100001 1 bs:3 sys #imm:5 1 0011110001 imm:5 swi #imm:6 1 001111001 imm:6
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 20 - mcu team lsi division system lsi business april 2000 clrsr bs:3 1 00111101000 0 bs:3 setsr bs:3 1 00111101000 1 bs:3 tstsr bs:3 1 00111101001 0 bs:3 nop 1 00111101001 1 0 0 0 break 1 00111101001 1 0 0 1 ld r0, sr 1 00111101001 1 0 1 0 ld sr, r0 1 00111101001 1 0 1 1 ret_fiq 1 00111101001 1 1 0 0 ret_irq 1 00111101001 1 1 0 1 ret_swi 1 00111101001 1 1 1 0 retd 1 00111101001 1 1 1 1 ld r0, spcl_fiq 1 00111101010 0 0 0 0 ld r0, spch_fiq 1 00111101010 0 0 0 1 ld r0, ssr_fiq 1 00111101010 0 0 1 0 reserved 1 00111101010 0 0 1 1 ld r0, spcl_irq 1 00111101010 0 1 0 0 ld r0, spch_irq 1 00111101010 0 1 0 1 ld r0, ssr_irq 1 00111101010 0 1 1 0 reserved 1 00111101010 0 1 1 1 reserved 1 00111101010 1 0 0 ld r0, ssr_swi 1 00111101010 1 0 1 0 reserved 1 00111101010 1 0 1 1 reserved 1 00111101010 1 1 ld spcl_fiq, r0 1 00111101011 0 0 0 0 ld spch_fiq, r0 1 00111101011 0 0 0 1 ld ssr_fiq, r0 1 00111101011 0 0 1 0 reserved 1 00111101011 0 0 1 1 ld spcl_irq, r0 1 00111101011 0 1 0 0 ld spch_irq, r0 1 00111101011 0 1 0 1 ld ssr_irq, r0 1 00111101011 0 1 1 0 reserved 1 00111101011 0 1 1 1 reserved 1 00111101011 1 0 0 ld ssr_swi, r0 1 00111101011 1 0 1 0 reserved 1 00111101011 1 0 1 1 reserved 1 00111101011 1 1
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 21 - mcu team lsi division system lsi business april 2000 reserved 1 0011110110 reserved 1 00111101110 ld an, pc 1 00111101111 0 an reserved 1 00111101111 1 jpf adr:22 1 001111100 adr[21:16] jpt adr:22 1 001111101 adr[21:16] jmp adr:22 1 001111110 adr[21:16] jsr adr:22 1 001111111 adr[21:16] ldc rn, @ai 1 0 1 0 rn 0 0 0 0 0 ai reserved 1 0 1 0 0 0 0 0 1 ld dn, ei 1 0100 dn 0001 0 ei ld en, di 1 0100 di 0001 1 en cmp eq, an, ai 1 0101 an 0001 0 ai ld an, ai 1 0101 an 0001 1 ai ldw rn, @[ai+disp:16] 1 0 1 0 rn 0 0 1 0 0 ai ldw @[an+disp:16], ri 1 0 1 0 ri 0 0 1 0 1 an ldb dn, @[ai+disp:16] 1 0100 dn 0011 0 ai ldb @[an+disp:16], di 1 0100 di 0011 1 an ldw an, @[ai+disp:16] 1 0101 an 0011 0 ai ldw @[an+disp:16], ai 1 0101 ai 0011 1 an cmp ge, dn, #imm:6 1 0100 dn 01 imm:6 add an, #imm:5 1 0101 an 010 imm:5 sub an, #imm:5 1 0101 an 011 imm:5 cmp eq, an, #imm:22 1 0100 an 10 imm[21:16] ld an, #imm:22 1 0101 an 10 imm[21:16] add an, ri 1 0100 an 1100 ri sub an, ri 1 0101 an 1100 ri mul uu, dn, di 1 0100 dn 1101 0 di mul us, dn, di 1 0100 dn 1101 1 di mul su, dn, di 1 0101 dn 1101 0 di mul ss, dn, di 1 0101 dn 1101 1 di pop rn[, rm] 1 0 1 0 rm 1 1 1 0 0 rn reserved 1 0100 1110 1 pop an[, am] 1 0101 am 1110 1 an push rn[, rm] 1 0 1 0 rm 1 1 1 1 0 rn
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 22 - mcu team lsi division system lsi business april 2000 reserved 1 0100 1111 1 push an[, am] 1 0101 am 1111 1 an bsrd eoffset:13 1 0 1 1 eoffset:13 bra ec:2, eoffset:8 1 100000 ec:2 eoffset:8 reserved 1 100001 brad ec:2, eoffset:8 1 100010 ec:2 eoffset:8 bnzd h, eoffset:8 1 100011h0 eoffset:8 reserved 1 100011 1 bra eoffset:11 1 10010 eoffset:11 brad eoffset:11 1 10011 eoffset:11 brf eoffset:11 1 10100 eoffset:11 brfd eoffset:11 1 10101 eoffset:11 brt eoffset:11 1 10110 eoffset:11 brtd eoffset:11 1 10111 eoffset:11 cld dn, imm:5 1 110000 imm:5 0 dn cld imm:5, di 1 110000 imm:5 1 di cop imm:13 1 1 1 imm:13 ? dn[15:0] : r0 ~ r7 ? h[15:0] : r6, r7 ? an[21:0] : a8 ~ a15, concatenation of en and rn ? en[5:0] : e8 ~ e15, ms 6-bit of an ? sp : equal to a15 ? ec:2 : ec0,ec1,ec2,ec3 ? disp : unsigned displacement ? eoffset : even signed offset ? edisp : even unsigned displacement 4. quick reference instruction op1 op2 operation flag add sub rn #imm:7 ri op1 <- op1 + op2 op1 <- op1 + ~op2 + 1 t=c, z0, z1,v ld rn #imm:8 #imm:16 ri op1 <- op2 z0, z1
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 23 - mcu team lsi division system lsi business april 2000 ldw rn @[sp+edisp:9] @[ai+edisp:5] @[ai+rj] @[ai+disp:16] op1 <- op2 - ldw @[sp+edisp:9] @[an+edisp:5] @[an+rm] @[ai+disp:16] ri op1 <- op2 - ldw an @[ai+edisp:5] @[ai+rj] @[ai+disp:16] op1 <- op2 - ldw @[an+edisp:5] @[an+rm] @[ai+disp:16] ai op1 <- op2 - ldb dn @[sp+disp:8] @[ai+disp:4] @[ai+rj] @[ai+disp:16] op1<-{8?h0,op2[7:0]} - ldb r0 @[a8+disp:8] op1<-{8?h0,op2[7:0]} - ldb @[sp+disp:8] @[an+disp:4] @[ai+rj] @[ai+disp:16] di op1 <- op2[7:0] - ldb @[a8+disp:8] r0 op1 <- op2[7:0] - adc sbc rn ri #imm:16 op1 <- op1 + op2 + t op1 <- op1 + ~op2 + t t=c,v, z0,z1 and or xor rn ri #imm:16 op1 <- op1 & op2 op1 <- op1 | op2 op1 <- op1 ^ op2 t=z, z0,z1 tst rn ri #imm:16 op1 & op2 t=z cmp ge cmp gt cmpu ge cmpu gt cmp eq rn ri #imm:16 op1 + ~op2 + 1, t=~n op1 + ~op2 + 1, t=~n&~z op1 + ~op2 + 1, t=c op1 + ~op2 + 1, t=c&~z op1 + ~op2 + 1, t=z t
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 24 - mcu team lsi division system lsi business april 2000 rr rl rrc srb sr sra slb rn - op1 <- {op1[0],op1[15:1]} op1 <- {op1[14:0],op1[15]} op1 <- {t,op1[15:1]} op1 <- {8?h00,op1[15:8]} op1 <- {0,op1[15:1]} op1 <- {op1[15],op1[15:1]} op1 <- {op1[7:0],8?h00} t=op1[0] t=op1[15] t=op1[0] t=op1[7] t=op1[0] t=op1[0] t= op1[8] dt rn op1 <- op1 + 0xffff t=z, z0,z1,v com rn op1 <- ~op1 t=z,z0, z1 incc decc com2 comc rn op1 <- op1 + t op1 <- op1 + 0xffff + t op1 <- ~op1 + 1 op1 <- ~op1 + t t=c,z0, z1 ext rn op1<-{8{op1[7]},op1[7:0]} z0, z1 jpf jpt jmp jsr ai addr:22 if(t==0) pc <- op1 if(t==1) pc <- op1 pc <- op1 a14 <- pc+(2|4), pc<-op1 - add rn #imm:16 op1 <- op1 + op2 t=c, z0,z1,v add sub an #imm:16 #imm:5 ri op1 <- op1 + op2 op1 <- op1 ? op2 - cmp eq dn #imm:8 op1 + ~op2 + 1 t=z and or xor tst r0 #imm:8 op1 <- op1 & {8?h00,op2} op1 <- op1 | {8?h00,op2} op1 <- op1 ^ {8?h00,op2} op1 & {8?h00,op2} t=z8 bitr bits bitc bitt @[a8+r1] bs:3 op1[op2] <- 0 op1[op2] <- 1 op1[op2] <- ~op1[op2] op1[op2] <- op1[op2] t= op1[op2] sys #imm:5 - da[4:0] <- op1 - swi #imm:6 - a14 <- pc+2, pc <- op2*4 ie, te
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 25 - mcu team lsi division system lsi business april 2000 clrsr setsr tstsr bs:3 - sr[op1] <- 0 sr[op1] <- 1 t <- ~sr[op1] - retd - - pc <- a14 - ld r0 sr spcl_fiq spch_fiq ssr_fiq spcl_irq spch_irq ssr_irq ssr_swi op1 <- op2 - ld sr spcl_fiq spch_fiq ssr_fiq spcl_irq spch_irq ssr_irq ssr_swi r0 op1 <- op2 ld an pc ai #imm:22 op1 <- op2 + 4 op1 <- op2 op1 <- op2 - cmp eq an ai #imm:22 op1 + ~op2 + 1 t=z22 ldc rn @ai op1 <- pm[op2] - ld rn ei op1 <- {10?h000, op2} - ld en ri op1 <- op2[5:0] - cmp ge dn #imm:6 op1 + ~op2 + 1 t=~n mul uu mul us mul su mul ss dn di op1<-{0,op1[7:0]} * {0,op2[7:0]} op1<-{0,op1[7:0]}*{op2[7],op2[7:0]} op1<-{op1[7],op1[7:0]}*{0,op2[7:0]} op1 <-{op1[7],op1[7:0]}* {op2[7],op2[7:0]} - pop rn rm op1<-@[sp+2], op2<-@[sp+4], sp<-sp+4 -
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 26 - mcu team lsi division system lsi business april 2000 push rn rm @[sp]<- op1,@[sp-2]<-op2,sp<-sp-4 - pop an am en<-@[sp+2], rn<-@[sp+4], em<- @[sp+6], rm<-@[sp+8], sp<-sp+8 - push an am @[sp]<-rn, @[sp-2]<-en, @[sp-4]<- rm, @[sp-6]<-em, sp<-sp-8 - bsrd eoffset:13 - a14 <- pc+2, pc <- pc + 2 + op1 - bra/brad ec:2 eoffset:8 if(ec:2 == 1) pc <- pc + 2 + op2 - bnzd r6 eoffset:8 if(z0 == 0) pc <- pc + 2 + op2 r6 <- r6 ? 1 z0 bnzd r7 eoffset:8 if(z1 == 0) pc <- pc + 2 + op2 r7 <- r7 ? 1 z1 bra/brad eoffset:11 - pc <- pc + 2 + op1 - brf/brfd eoffset:11 - if(t==0) pc <- pc + 2 + op1 - brt/brtd eoffset:11 - if(t==1) pc <- pc + 2+op1 - cld dn imm:5 op1 <- coprocessor[op2] - cld imm:5 di coprocessor[op1] <- op2 cop imm:13 - copir <- op2
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 27 - mcu team lsi division system lsi business april 2000 adc (1) adc rn, ri add with carry register description the adc (add with carry register) instruction is used to synthesize 32-bit addition. if register pairs r0, r1 and r2, r3 hold 32-bit values (r0 and r2 hold the least-significant word), the following instructions leave the 32-bit sum in r0, r1: add r0, r2 adc r1, r3 the instruction adc r0, r0 produces a single-bit rotate left with carry (17-bit rotate through the carry) on r0. adc adds the value of register rn, and the value of the carry flag (stored in the t bit), and the value of register ri, and stores the result in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 0 1 0 ri operation rn := rn + ri + t bit t bit := carry from (rn + ri + t bit) v flag := overflow from (rn + ri + t bit) if(rn == r6/r7) z0/z1 flag := ((rn + ri + t) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 28 - mcu team lsi division system lsi business april 2000 adc (2) adc rn, # add with carry immediate description the adc (add with carry immediate) instruction is used to synthesize 32-bit addition with an immediate operand. if register pair r0, r1 holds a 32-bit value (r0 holds the least-significant word), the following instructions leave the 32-bit sum with 87653456h in r0, r1: add r0, #3456h adc r1, #8765h adc adds the value of register rn, and the value of the carry flag (stored in the t bit), and the 16-bit immediate operand, and stores the result in register rd. the t bit and the v flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 0 1 1 1 1 rn operation rn := rn + + t bit t bit := carry from (rn + + t bit) v flag := overflow from (rn + + t bit) if(rn == r6/r7) z0/z1 flag := ((rn + ) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instructions, therefore, fetching of adc rn, takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 29 - mcu team lsi division system lsi business april 2000 add (1) add rn, ri add register description the add (add register) instruction is used to add two 16-bit values in registers. 32-bit addition can be achieved by executing adc instruction in pair with this instruction (see page 27). add adds the value of register rn, and the value of register ri, and stores the result in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 0 0 0 ri operation rn := rn + ri t bit := carry from (rn + ri) v flag := overflow from (rn + ri) if(rn == r6/r7) z0/z1 flag := ((rn + ri) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 30 - mcu team lsi division system lsi business april 2000 add (2) add rn, # add small immediate description this form of add instruction is used to add a 7-bit (positive) immediate value to a register add adds the value of register rn, and the value of , and stores the result in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 8 7 6 0 0 0 0 0 rn 0 operation rn := rn + t bit := carry from (rn + ) v flag := overflow from (rn + ) if(rn == r6/r7) z0/z1 flag := ((rn + ) == 0) exceptions none. notes is an unsigned amount.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 31 - mcu team lsi division system lsi business april 2000 add (3) add rn, # add immediate description the add (add immediate) inst ruction is used to add a 16-bit immediate value to a register. 32-bit addition or subtraction can be achieved by executing adc or sbc instruction in pair with this instruction (see page 28 and 99 for examples). add adds the value of register rn, and the value of , and stores the result in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 0 1 1 1 1 rn operation rn := rn + t bit := carry from (rn + ) v flag := overflow from (rn + ) if(rn == r6/r7) z0/z1 flag := ((rn + ) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instructions, therefore, fetching of add rn, takes 2 cycles. the instruction ?sub rn, #? does not exist. the result of ?sub rn, #? instruction is identical with the result of ?add rn, #(2?s complement of )? except when is zero. in that case, ?sub rn, #? can be used.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 32 - mcu team lsi division system lsi business april 2000 add (4) add an, ri add extended register description the add (add extended register) instruction is used to add a 16-bit unsigned register value to a 22-bit register. this instruction adds the value of 16-bit register ri, and the value of 22-bit register an, and stores the result in register an. 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 1 0 0 an 1 1 0 0 ri operation an := an + ri exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 33 - mcu team lsi division system lsi business april 2000 add (5) add an, # add immediate to extended register description this form of add instruction is used to add a 16-bit unsigned immediate value to a 22-bit register. this instruction adds the value of to the value of an, and stores the result in register an 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 0 0 0 0 1 1 1 1 1 0 an operation an := an + exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 34 - mcu team lsi division system lsi business april 2000 add (6) add an, # add 5-bit immediate to extended register description this form of add instruction is used to add a 5-bit unsigned immediate value to a 22-bit register. this instruction adds the value of 5-bit immediate , and the value of 22- bit register an, and stores the result in register an. 15 14 13 12 11 10 8 7 6 5 4 0 1 0 1 0 1 an 0 1 0 operation an := an + exceptions none. notes is an unsigned amount.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 35 - mcu team lsi division system lsi business april 2000 and (1) and rn, ri and register description the and (and register) instruction is us ed to perform bitwise and operation on two values in registers, rn and ri. the result is stored in register rn. the t bit is updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 1 0 0 ri operation rn := rn & ri t bit := ((rn & ri) == 0) if(rn == r6/r7) z0/z1 flag := ((rn & ri) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 36 - mcu team lsi division system lsi business april 2000 and (2) and r0, # and small immediate description the and (and small immediat e) instruction is used to perform an 8-bit bitwise and operation on two values in register r0 and . the result is stored in register r0. the t bit is updated based on the result. 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 0 0 0 operation r0 := r0 & t bit := ((r0 & )[7:0] == 0) exceptions none. notes the register used in this operation is fixed to r0. therefore, the operand should be placed in r0 before this instruction exec utes. is zero-extended to a 16-bit value before operation.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 37 - mcu team lsi division system lsi business april 2000 and (3) and rn, # and large immediate description this type of and instruction is used to perform bitwise and operation on two values in register rn and . the result is stored in register rn. the t bit is updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 0 1 1 1 1 rn operation rn := rn & t bit := ((rn & ) == 0) if(rn == r6/r7) z0/z1 flag := ((rn & ) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 38 - mcu team lsi division system lsi business april 2000 bitop bitop @[a8+r1], # bit operation description the bitop (bit operation) instruction is us ed to perform a bit operation on an 8-bit memory value. the allowed operations include reset (bitr), set (bits), complement (bitc), and test (bitt). bitop fetches the value of memory location specified by @(a8+r1), performs the specified operation on the specified bit, and stores the result back into the same memory location 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 0 0 0 op operation temp := mem[a8+r1] t bit := ~temp[] if (bitop != bitt) { result := bitop(temp, ) mem[a8+r1] := result } here, bitop is bitr (op == 00) | bits (01) | bitc (10) | bitt (11). the bit location of these operations is specified by . exceptions none. notes the address used to access data memory is obtained from the addition of two registers a8 and r1. no other registers can be used for this address calculation.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 39 - mcu team lsi division system lsi business april 2000 bnzd bnzd h, branch not zero with autodecrement description the bnzd (branch not zero with delay slot) instruction is used to change the program flow when the specified register value does not evalua te to zero. after evaluation, the value in register is auto matically decremented. a typical usage of this instruction is as a backward branch at the end of a loop. loop: ... bnzd r6, loop // if (z0 != 0) go back to loop add r4, 3 // delay slot in the above example, r6 is used as the loop counter. after specified loop iterations, bnzd is not taken and the control will come out of the loop, and r6 will have -1. for a loop with ?n? iterations, the counter register used should be initially set to ?(n-1)?. bnzd has a single delay slot; the instruction that immediately follows bnzd will be executed always regardless of whether bnzd is taken or not. 15 14 13 12 11 10 9 8 7 6 0 1 1 0 0 0 1 1 h 0 operation if(h == r6) { if(z0 != 0) pc := pc + 2 + r6 := r6 ? 1 z0 := ((r6-1) == 0) } else { // h == r7 same mechanism as the case r6 } h is a register specifier denoting either r6 or r7. exceptions none. notes when bnzd checks if h is zero by looking up the z0 (for r6) or z1 (for r7) bit in sr, these flags are updated as bnzd decrem ents the value of the register. for the first iteration, however, the user is responsible for resetting the flag, z0 or z1, before the loop starts execution.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 40 - mcu team lsi division system lsi business april 2000 br brtype conditional branch description the br (conditional branch) instruction is used to change the program flow conditionally or unconditionally. the allowed forms of the instruction include bra (always), brad (always with delay slot), brt (when t bit is set), brtd (when t bit is set, with delay slot), brf (when t bit is clear), and brfd (when t bit is clear, with delay slot). the branch target address is calculated by 1. sign-extending to 22 bits 2. adding this to the pc (which contains the address of the branch instruction plus 1) 15 14 13 12 11 10 9 0 1 1 0 d operation if (condition) pc := pc + 2 + here, the field determines whether this branch is bra (01), brf (10), or brt (11). if d is set, the branch instru ction has one branch delay slot, meaning that the instruction following the branch w ill be executed always, regardless of the branch outcome. if d is clear, the immediately following instruction is not executed if the branch is taken. exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 41 - mcu team lsi division system lsi business april 2000 bra ec bra(d) ec:2 branch on external condition description the bra ec (branch on external condition) instruction is used to change the program flow when a certain external condition is set. a typical usage of this instruction is to branch after a coprocessor operation as shown below: cop nop nop bra ec0 overflow ... overflow: ... ... the bra ec instruction checks the specified external condition (instead of checking the t bit as other branch instructions, see page 40) and branch to the specified program address. there can be up to 4 external conditions, specified by the field in the instruction. 15 14 13 12 11 10 9 8 7 6 0 1 1 0 0 0 d 0 operation if (externalcondition_n == true) pc := pc + 2 + exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 42 - mcu team lsi division system lsi business april 2000 break break break description the break instruction suspends the calm risc core for 1 cycle by keeping pc from increasing. processor resumes execution after 1 cycle. this instruction is used for debugging purposes only and thus should not be used in normal operating modes. a core signal nbrk is asserted low for the cycle. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 operation no operation with pc suspended for a single cycle. exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 43 - mcu team lsi division system lsi business april 2000 bsrd bsrd branch subroutine with delay slot description the bsrd (branch subroutine with delay slot) instruction is used to change the program flow to a subroutine by assigning the address of the subroutine to pc after saving the return address (pc+4) in the link register, or a14. the address of the subr outine is calculated by: 1. sign-extending to 22 bits 2. adding this to the pc (which contains the address of the branch instruction plus 1) after executing the subroutine, the program flow can return back to the instruction that follows the bsrd instruction by setting pc with the value stored in a14 (see jmp ai instruction in page 58 and ret instruction in page 91). this instruction has a delay slot; the instruction that immediately follows bsrd will be always executed. 15 14 13 12 11 0 1 0 1 1 operation a14 := pc + 4 pc := pc + 2 + exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 44 - mcu team lsi division system lsi business april 2000 cld cld dn, / cld , di coprocessor load description the cld (coprocessor load) instruction is used to transfer data from and to coprocessor by generating the core signals ncldid and cldwr. the content of da[4:0] is , the address of coproc essor register to be read or written. when a data item is read from coprocessor (cld dn, ), it is stored in dn. when a data item is written to coprocessor, it should be prepared in di. 15 14 13 12 11 10 8 7 6 5 4 0 1 1 1 0 0 0 0 imm:5 m dn/di operation (m == 0, read) da[4:0] := ncldid := 0 cldwr := 0 dn := () (m == 1, write) da[4:0] := ncldid := 0 cldwr := 1 () := di exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 45 - mcu team lsi division system lsi business april 2000 clrsr clrsr bs:3 clear sr description the clrsr (clear sr) instruction is used to clear a specified bit in sr as follows: clrsr fe / ie / te / v / z0 / z1 / pm to clear the t bit, on e can do as follows: cmp gt, r0, r0 to turn on a specified bit in sr, the setsr instruction (in page 100 ) is used. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 0 0 0 0 operation sr[] := 0 exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 46 - mcu team lsi division system lsi business april 2000 cmp (1) cmpmode rn, ri compare register description the cmp (compare register) instruction is used to compare two values in registers rn and ri. the allowed modes include ge (greater or equal), gt (greater than), uge (unsigned greater or equal), ugt (unsig ned greater than), and eq (equal). cmp subtracts the value of ri from the value of rn and performs comparison based on the result. the contents of rn an d ri are not changed after this operation. the t bit is updated for later reference. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 1 ri operation temp := rn - ri t bit := ~negative if ( == ge) ~negative && ~zero if ( == gt) carry if ( == uge) carry && ~zero if ( == ugt) zero if ( == eq) encoding: ge (000), gt (001), uge (010), ugt (011), and eq (100). exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 47 - mcu team lsi division system lsi business april 2000 cmp (2) cmpmode rn, # compare immediate description the cmp (compare immediate) instructi on is used to compare two values in register rn and . the allowed mode s include ge (greater or equal), gt (greater than), uge (unsigned greater or equal), ugt (unsig ned greater than), and eq (equal). cmp subtracts the value of from the value of rn and performs comparison based on the result. the conten ts of rn is not changed, however, after this operation. the t bit is updated for later reference. 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 0 0 1 1 1 1 1 rn operation temp := rn - t bit := ~negative if ( == ge) ~negative && ~zero if ( == gt) carry if ( == uge) carry && ~zero if ( == ugt) zero if ( == eq) encoding: ge (000), gt (001), uge (010), ugt (011), and eq (100). exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instructions, therefore, fetching of cmpmode # takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 48 - mcu team lsi division system lsi business april 2000 cmp (3) cmp ge, dn, # compare short immediate description the cmp (compare immediate) instruction is used to perform signed-comparison of the register dn and an unsigned immediate value . dn is one of the registers from r0 to r7. cmp subtracts the value of from the value of dn and performs signed-comparison based on the result. the contents of dn is not changed, however, after this operation. the t bit is updated for later reference. 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 1 0 0 dn 0 1 imm:6 operation t bit := ~negative of (rn - ) exceptions none. notes none
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 49 - mcu team lsi division system lsi business april 2000 cmpeq (1) cmp eq, an, ai compare equal extended register description the cmp eq (compare equal extended register) instruction is used to compare two values in registers an and ai. this instruction is a restricted form of more general cmpmode instructions for a 22-bit equality comparison between register values. 15 14 13 12 11 10 8 7 6 5 4 3 2 0 1 0 1 0 1 an 0 0 0 1 0 ai operation t bit := (an == ai) an or ai refers to registers from a8 to a15 with their 6-bit extensions. exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 50 - mcu team lsi division system lsi business april 2000 cmpeq (2) cmp eq, dn, # compare equal small immediate description the cmp eq (compare equal small immediate) instruction is used to compare two values in register dn and . is zero-extended to 16 bits before comparison. this instruction is a restricted form of more general cmpmode instructions for an 8-bit equality comparison between a register value and an immediate value. 15 14 13 12 11 10 8 7 0 1 0 0 1 0 dn operation t bit := ((dn - ) == 0) dn refers to registers r0 - r8. exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 51 - mcu team lsi division system lsi business april 2000 cmpeq (3) cmp eq an, # compare equal large immediate description the cmp eq (compare equal large immedi ate) instruction is used to compare two values in register an and . this instruction is a restricted form of more general cmpmode instructions for a 22-bit equality comparison between a register value and an immediate value. 15 14 13 12 11 10 8 7 6 5 0 1 0 1 0 0 an 1 0 [21:16] operation t bit := zero from (an - ) an refers to registers from a8 to a15 with their 6-bit extensions. exceptions none. notes this is a 2-word instruction, where the 16-bit immediate ([15:0]) follows the instruction word shown above. unlike 1-word instructions, therefore, fetching of cmp eq takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 52 - mcu team lsi division system lsi business april 2000 com commode rn complement description the com (complement) instruction is used to compute 1?s or 2?s complement of a register value rn. utilizing various modes, 32-bit complement operation can be done. if register pair r0, r1 holds a 32-bit value (r0 holds the least-significant word), the following instructions leave the 32-bit 2?s complement in r0, r1: com2 r0 // 2?s complement comc r1 // 2?s complement with carry com computes the 1?s complement of the value of register rn. com2 computes the 2?s complement, and comc computes the 2?s complement value when t bit has been set. if t bit is clear, com2 is equivalent to com. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 1 1 1 1 0 rn operation if ( == 00) { // com rn := ~rn t bit := (rn == 0) } if ( == 01) { // com2 rn := ~rn + 1 t bit := carry from (~rn + 1) } if ( == 10) { // comc rn := ~rn + t bit t bit := carry from (~rn + t) } encoding of : 00: com, 01: com2, 10: comc if(rn == r6/r7) z0/z1 := zero flag of the result. exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 53 - mcu team lsi division system lsi business april 2000 cop cop coprocessor description the cop (coprocessor) instruction is us ed to perform a coprocessor operation, specified by . certain coprocessor operations set external conditions, upon which branches can be executed (see brecn instructions, from page 41). the should be greater or equal to 0x200. 15 14 13 12 0 1 1 1 operation perform a coprocessor operation by placing signals on core output pins as follows: core output signal copir[12:0] := core output signal ncopid := low exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 54 - mcu team lsi division system lsi business april 2000 decc decc rn decrement with carry description the decc (decrement with carry) instruction is used to synthesize 32-bit decrement. if register pa ir r0, r1 holds a 32-bit value (r0 holds the least- significant word), the following instructions leave the 32-bit decremented value in r0, r1: dec r0 // this is implemented by add r0, -1 decc r1 decc decrements the value of rn by 1 only if the carry flag (stored in the t bit) is clear, and stores the result back in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 0 1 1 1 1 1 0 rn operation rn := rn - 1 + t bit t bit := carry from (rn - 1 + t bit) v flag := overflow from (rn -1 + t bit) if(rn == r6/r7) z0/z1 := ((rn ? 1 + t) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 55 - mcu team lsi division system lsi business april 2000 dt dt rn decrement and test description the dt (decrement and test) instruction is used to decrement the value of a specified register and test it. this inst ruction provides a compact way to control register indexing for loops. the t bit and the v flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 0 0 1 1 1 1 0 rn operation rn := rn - 1 t bit := ((rn - 1) == 0) v flag := overflow from (rn - 1) if(rn == r6/r7) z0/z1 := ((rn ? 1) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 56 - mcu team lsi division system lsi business april 2000 ext ext rn sign-extend description the ext (sign extend) instruction is used to sign-extend an 8-bit value in rn. this instruction copies rn[7] to rn[15:8]. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 1 1 1 1 1 1 0 rn operation all bits from rn[15] to rn[8] := rn[7] if(rn == r6/r7) z0/z1 := (result == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 57 - mcu team lsi division system lsi business april 2000 incc incc rn increment with carry description the incc (increment with carry) instruction is used to synthesize 32-bit increment. if register pair r0, r1 ho lds a 32-bit value (r0 holds the least- significant word), the following instructions leave the 32-bit incremented value in r0, r1: inc r0 // will be replaced by add r0, 1 incc r1 incc increments the value of rn by 1 only if the carry flag (stored in the t bit) is set, and stores the result back in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 0 1 0 1 1 1 0 rn operation rn := rn + t bit t bit := carry from (rn + t bit) v flag := overflow from (rn + t bit) if(rn == r6/r7) z0/z1 := ((rn + t0) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 58 - mcu team lsi division system lsi business april 2000 jmp (1) jpf/jpt/jmp/jsr ai jump register description the jump register instructions change the program flow by assigning the value of register ai into pc. jpf and jpt are conditional jumps that check the t bit to determine whether or not to jump to the target address. jmp unconditionally jumps to the target. jsr is an unconditional jump but saves the return address (the immediately following instruction to jsr) in the link register, a14. at the end of each subroutine, jmp a14 will change the program flow back to the original call site. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 0 0 1 1 m [1] 1 1 1 0 m [0] ai operation (m == 00, jpf) if (t bit == false) pc := ai (m == 01, jpt) if (t bit == true) pc := ai (m == 10, jmp) pc := ai (m == 11, jsr) a14 := pc + 2 pc := ai exceptions none. notes there is no delay slot for these instruc tions. therefore, when conditional branch jpf or jpt is taken, the instruction in the pipeline which is fetched from pc+2 will be squashed. in case of jmp and jsr (a lways taken), the following instruction fetched will be always squashed.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 59 - mcu team lsi division system lsi business april 2000 jmp (2) jpf/jpt/jmp/jsr jump immediate description the jump immediate instructions change the program flow by assigning the value of into pc. jpf and jpt are conditional jumps that check the t bit to determine whether or not to jump to the target address. jmp unconditionally jumps to the target. jsr is an unconditional jump but saves the return address (the immediately following instruction to jsr) in the link register, a14. at the end of each subroutine, jmp a14 will change the program flow back to the original call site. 15 14 13 12 11 10 9 8 7 6 5 0 1 0 0 1 1 1 1 1 [21:16] operation ( == 00, jpf) if (t bit == false) pc := ( == 01, jpt) if (t bit == true) pc := ( == 10, jmp) pc := ( == 11, jsr) a14 := pc + 4 pc := exceptions none. notes these are 2-word instruc tions, where the 16-bit immediate ([15:0]) follows the instruction word shown above. as fetching of a 2-word instruction takes 2 cycles, no later instructions will be in processor pipeline when the branch is taken (thus no squashing).
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 60 - mcu team lsi division system lsi business april 2000 ld (1) ld rn, ri load register description the ld (load register) instruction is used to transfer a register value to a register. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 1 1 0 1 ri operation rn := ri if(rn == r6/r7) z0/z1 := (ri == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 61 - mcu team lsi division system lsi business april 2000 ld (2) ld an, ai load extended register description this form of ld instruction (load extended register) is used to load a 22-bit register value to a 22-bit register. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 1 0 1 an 0 0 0 1 1 ai operation an := ai exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 62 - mcu team lsi division system lsi business april 2000 ld (3) ld rn, # load short immediate description the ld (load short immediate) instruction is used to load an 8-bit immediate value to a register. 15 14 13 12 11 8 7 0 0 0 0 1 rn operation rn[15:8] := 0, rn[7:0] := if(rn == r6/r7) z0/z1 := ( == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 63 - mcu team lsi division system lsi business april 2000 ld (4) ld rn, # load immediate description this form of ld instruction (load immediate) is used to load a 16-bit immediate value to a register. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 1 1 0 1 1 1 1 1 rn operation rn := if(rn == r6/r7) z0/z1 := ( == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 64 - mcu team lsi division system lsi business april 2000 ld (5) ld an, # load large immediate description this form of ld instruction (load large immediate) is used to load a 22-bit immediate value to an extended register an. 15 14 13 12 11 10 8 7 6 5 0 1 0 1 0 1 an 1 0 [21:16] operation an := exceptions none. notes this is a 2-word instruction, where the 16-bit immediate ([15:0]) follows the instruction word shown above. unlike 1-word instructions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 65 - mcu team lsi division system lsi business april 2000 ld rext ld dn, ei / ld en, di load register extension description the ld rext (load register extension) inst ructions are used to transfer a register value to and from a 6-bit extension register. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 0 dn(or di) 0 0 0 1 m ei (or en) operation (m == 0, ld dn, ei) dn := ei (zero-extended to 16 bits) (m == 1, ld en, di) en := di (lower 6 bits only) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 66 - mcu team lsi division system lsi business april 2000 ldb (1) ldb dn, @[ai+] / ldb @[an+], di load byte register disp. description the ldb (load byte register displacement) instruction is used to load a byte from or to data memory at the location specified by the register ai and a 4-bit displacement. 15 14 13 12 11 10 8 7 6 4 3 0 0 1 1 m 0 dn or di 0 ai or an operation (m == 0, ldb dn, @[ai+]) dn := dm[(ai+)] (m == 1, ldb @[an+], di) dm[(an+)] := di exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 67 - mcu team lsi division system lsi business april 2000 ldb (2) ldb dn, @[ai+] / ldb @[an+], di load byte register large disp. description the ldb (load byte register large displacement) instruction is used to load a byte from or to data memory at the loca tion specified by the register ai and a 16- bit displacement. 15 14 13 12 11 10 8 7 6 5 4 3 2 0 1 0 1 0 0 dn or di 0 0 1 1 m ai or an operation (m == 0, ldb dn, @[ai+]) dn := dm[(ai+)] (m == 1, ldb @[an+], di) dm[(an+)] := di exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 68 - mcu team lsi division system lsi business april 2000 ldb (3) ldb dn, @[ai+rj] / ldb @[an+rm], di load byte register indexed description the ldb (load byte register indexed) instruction is used to load a byte from or to data memory at the location specified by the register ai (or an) and the second register rj (or rm). 15 14 13 12 11 10 8 7 6 4 3 0 0 1 1 m 0 dn or di 1 ai or an rj or rm operation (m == 0, ldb dn, @[ai+rj]) dn := dm[(ai+rj] (m == 1, ldb @[an+rm], di) dm[(an+rm)] := di exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 69 - mcu team lsi division system lsi business april 2000 ldb (4) ldb r0, @[a8+] / ldb @[a8+], a8 load byte to r0 register disp. description the ldb (load byte to r0 register displacement) instruction is used to load a byte from or to data memory at the location specified by the register a8 and an 8- bit displacement. 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 1 0 m operation (m == 0, ldb r0, @[a8+]) r0 := dm[(a8+] (m == 1, ldb @[a8+], r0) dm[(a8+)] := r0 exceptions none. notes this single-word instruction allows a user to access a wider range of data memory than the ldb (1) instruction by providing a larger displacement, at the expense of the restrictions that only the r0 and a8 registers are used for data transfer and address computation.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 70 - mcu team lsi division system lsi business april 2000 ldc ldc rn, @ai load code description the ldc instruction is used to transfer a register value from the program memory. the program memory address is specified by the 22-bit register an. ldc is useful to look up the data stored in program memory, such as the coefficient table for certain numerical algorithms. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 rn 0 0 0 0 0 ai operation rn := pm[ai] exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 71 - mcu team lsi division system lsi business april 2000 ld pc ld an, pc load program counter description the ld pc (load program counter) instructio n is used to transfer the value of pc into a 22-bit register an. this instruction provides a way to implement position independent code (pic) on calmrisc16 even in the absence of general virtual memory support. after executing this instruction, an will be used to compute a pc-relative location of a data item or a code section. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 1 1 1 0 an operation an := pc + 4 exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 72 - mcu team lsi division system lsi business april 2000 ld svr (1) ld r0, spcl_* / ld r0, spch_* / ld r0, ssr_* load from saved register description the ld svr (load from saved register) instructions are used to transfer a value from the specified interrupt register, e.g., ssr_fiq. only r0 register is used for this data transfer. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 1 1 1 1 0 1 0 1 0 operation r0 := encoding for (register specifier): 0000: spcl_fiq, 0001: spch_fiq, 0010: ssr_fiq, 0100: spcl_irq, 0101: spch_irq, 0110: ssr_irq, 1010: ssr_swi exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 73 - mcu team lsi division system lsi business april 2000 ld svr (2) ld spcl_*, r0 / ld spch_*, r0 / ld ssr_*, r0 load to saved register description the ld svr (load to saved register) instru ctions are used to transfer a value to the specified interrupt regist er, e.g., ssr_fiq. only r0 register is used for this data transfer. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 1 1 1 1 0 1 0 1 1 operation := r0 encoding for (register specifier): 0000: spcl_fiq, 0001: spch_fiq, 0010: ssr_fiq, 0100: spcl_irq, 0101: spch_irq, 0110: ssr_irq, 1010: ssr_swi exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 74 - mcu team lsi division system lsi business april 2000 ld sr ld r0, sr / ld sr, r0 load status register description the ld sr (load status register) instruction is used to transfer a value to and from sr. only r0 register is used for this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 m operation (m == 0, ld r0, sr) r0 := sr (m == 1, ld sr, r0) sr := r0 exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 75 - mcu team lsi division system lsi business april 2000 ldw (1) ldw rn, @[sp+] / ldw @[sp+], ri load word stack disp. description the ldw (load word stack displacement) instruction is used to load a word from or to data memory at the location sp ecified by the sp register (or a15) and an even 9-bit displacement. , from 0 to 510, is encoded into 8-bit displacement by dropping th e least significant bit. 15 14 13 12 11 8 7 0 0 0 1 m rn or ri operation (m == 0, ldw rn, @[sp+]) rn := dm[(sp + )] (m == 1, ldw @[sp+], ri) dm[(sp + )] := ri exceptions none. notes for memory transfer per word, the (byte) address need to be aligned to be even. thus, if (sp + ) is an odd numb er, it will be made even by clearing the least significant bit. can denote an even number from 0 to 510.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 76 - mcu team lsi division system lsi business april 2000 ldw (2) ldw rn, @[ai+] / ldw @[an+], ri load word register small disp. description the ldw (load word register displacement) instruction is used to load a word from or to data memory at the location speci fied by the register ai and a 5-bit even displacement from 0 to 30. is en coded to 4-bit numbe r by dropping the least significant bit. 15 14 13 12 11 8 7 6 4 3 0 0 1 0 m rn or ri 0 ai or an operation (m == 0, ldw rn, @[ai+]) rn := dm[(ai + )] (m == 1, ldw @[an+], ri) dm[(an + )] := ri exceptions none. notes for memory transfer per word, the (byte) address need to be aligned to be even. thus, if (ai + ) is an odd number, it will be made even by clearing the least significant bit. can denote an even number from 0 to 30.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 77 - mcu team lsi division system lsi business april 2000 ldw (3) ldw rn, @[ai+] / ldw @[an+], ri load word register disp. description the ldw (load word register large displ acement) instruction is used to load a word from or to data memory at the loca tion specified by the register ai and a 16- bit displacement. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 rn or ri 0 0 1 0 m ai or an operation (m == 0, ldw rn, @[ai+]) rn := dm[(ai + )] (m == 1, ldw @[an+], ri) dm[(an + )] := ri exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles. for memory transf er per word, the (byte) address need to be aligned to be even. thus, if (ai + ) is an odd number, it will be made even by clearing the least significant bit.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 78 - mcu team lsi division system lsi business april 2000 ldw (4) ldw rn, @[ai+rj] / ldw @[an+rm], ri load word register indexed description the ldw (load word register indexed) instruction is used to load a word from or to data memory at the location specified by the register ai (o r an) and the second register rj (or rm), which is an unsigned value. 15 14 13 12 11 8 7 6 4 3 0 0 1 0 m rn or ri 1 ai or an rj or rm operation (m == 0, ldw rn, @[ai+rj]) rn := dm[(ai+rj] (m == 1, ldw @[an+rm], ri) dm[(an+rm)] := ri exceptions none. notes for memory transfer per word, the (byte) address needs to be aligned to be even. thus, if (ai + rj) or (an + rm) is an odd number, it will be made even by clearing the least significant bit.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 79 - mcu team lsi division system lsi business april 2000 ldw (5) ldw an, @[ai+] / ldw @[ai+], an load word register small disp. description the ldw (load word register displacement) instruction is used to load 2 word from or to data memory at the location speci fied by the register ai and a 5-bit even displacement from 0 to 30. is en coded to 4-bit numbe r by dropping the least significant bit. 15 14 13 12 11 8 7 6 4 3 0 0 1 1 m 1 an 0 ai operation (m == 0, ldw an, @[ai+]) en := dm[(ai + )] rn := dm[(ai + + 2)] (m == 1, ldw @[ai+], an) dm[(ai + )] := en dm[(ai + + 2)] := rn exceptions none. notes for memory transfer per word, the (byte) address need to be aligned to be even. thus, if (ai + ) is an odd number, it will be made even by clearing the least significant bit. can denote an even number from 0 to 30.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 80 - mcu team lsi division system lsi business april 2000 ldw (6) ldw an, @[ai+] / ldw @[ai+], an load word register disp. description the ldw (load word register large displacement) instruction is used to load 2 word from or to data memory at the loca tion specified by the register ai and a 16- bit displacement. 15 14 13 12 11 8 7 6 5 4 3 2 0 1 0 1 0 1 an 0 0 1 1 m ai operation (m == 0, ldw an, @[ai+]) en := dm[(ai + )] rn := dm[(ai + + 2)] (m == 1, ldw @[ai +], an) dm[(ai + )] := en dm[(ai + + 2)] := rn exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles. for memory transf er per word, the (byte) address need to be aligned to be even. thus, if (ai + ) is an odd number, it will be made even by clearing the least significant bit.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 81 - mcu team lsi division system lsi business april 2000 ldw (7) ldw an, @[ai+rj] / ldw @[ai+rj], an load word register indexed description the ldw (load word register indexed) instruction is used to load 2 word from or to data memory at the location specified by the register ai and the second register rj, which is an unsigned value. 15 14 13 12 11 8 7 6 4 3 0 0 1 1 m 1 an 1 ai rj operation (m == 0, ldw an, @[ai + rj]) en := dm[(ai + rj)] rn := dm[(ai + rj + 2)] (m == 1, ldw @[ai + rj], an) dm[(ai + rj)] := en dm[(ai + rj + 2)] := rn exceptions none. notes for memory transfer per word, the (byte) address needs to be aligned to be even. thus, if (ai + rj) is an odd number, it will be made even by clearing the least significant bit.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 82 - mcu team lsi division system lsi business april 2000 mul mul mode, dn, di multiplication description the instruction mul performs 8x8 multiplica tion of the least si gnificant byte of dn and the least significant byte of di. dn and di are registers from r0 to r7. the 16-bit multiplication result is written back to dn. the mode is one of uu, us, su, ss. the mode indicates each operand is signed value or unsigned value. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 m1 dn 1 1 0 1 m2 di operation if(m1 == 0 && m2 == 0) // mode = uu dn := lower 16 bits of ({0,dn[7:0]} * {0, di[7:0]}) else if(m1 == 0 && m2 == 1) // mode == us dn := lower 16 bits of ({0,dn[7:0]} * {di[7],di[7:0]}) else if(m1 == 1 && m2 == 0) // mode == su dn := lower 16 bits of ({dn[7],dn[7:0]} * {0,di[7:0]}) else // mode == ss dn := lower 16 bits of ({dn [7],dn[7:0]} * {di[7],di[7:0]}) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 83 - mcu team lsi division system lsi business april 2000 nop nop no operation description the nop (no operation) instruction does not perform any operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 0 0 0 0 operation none. exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 84 - mcu team lsi division system lsi business april 2000 or (1) or rn, ri or register description the or (or register) instruction is used to perform bitwise or operation on two values in registers, rn and ri. the result is stored in register rn. the t bit is updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 1 0 1 ri operation rn := rn | ri t bit := ((rn | ri) == 0) if(rn == r6/r7) z0/z1 := ((rn|ri) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 85 - mcu team lsi division system lsi business april 2000 or (2) or r0, # or small immediate description the or (or small immediate) instruction is used to perform bitwise or operation on two values in register r0 and . the result is stored in register r0. the t bit is updated based on the result. 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 0 0 1 operation r0 := r0 | t bit := ((r0 | )[7:0] == 0) exceptions none. notes the register used in this operation is fixed to r0. therefore, the operand should be placed in r0 before this instruction exec utes. is zero-extended to a 16-bit value before operation.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 86 - mcu team lsi division system lsi business april 2000 or (3) or rn, # or large immediate description this type of or instruction is used to perform bitwise or operation on two values in register rn and . the result is stored in register r0. the t bit is updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 1 1 1 1 1 rn operation rn := rn | t bit := ((rn | ) == 0) if(rn == r6/r7) z0/z1 := ((rn | ) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 87 - mcu team lsi division system lsi business april 2000 pop(1) pop rn, rm / pop rn load register from stack description the pop instruction load one or two 16-bit data from software stack to general registers. in the instruction of ?pop rn , rm?, there are some restrictions on rn and rm. - rn and rm should not be r15. - if rn is one of the 8 registers from r0 to r7, rm should also be one of them. if rn is one of the registers from r8 to r14, rm should also be one of them. for example, ?pop r7, r8? is illegal. - if rn is the same as rm, pop operation occurs only once. ?pop rn, rn? is equivalent to ?pop rn?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 rm 1 1 1 0 0 rn operation if(rn == rm) { // pop rn rn := dm[sp + 2] sp := sp + 2 } else { rn := dm[sp + 2] rm := dm[sp + 4] sp := sp + 4 } exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 88 - mcu team lsi division system lsi business april 2000 pop(2) pop an, am / pop an load register from stack description the pop instruction load one or two 22- b it data from software stack to extended registers. in the instruction of ?pop an, am?, there are some restrictions on an and am. - an and am should not be a15. - if an is the same as am, pop operation occurs only once. ?pop an, an? is equivalent to ?pop an?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 am 1 1 1 0 1 an operation if(an == am) { // pop an en := lower 6 bits of dm[sp + 2] rn := dm[sp + 4] sp := sp + 4 } else { en := lower 6 bits of dm[sp + 2] rn := dm[sp + 4] em := lower 6 bits of dm[sp + 6] rm := dm[sp + 8] sp := sp + 8 } exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 89 - mcu team lsi division system lsi business april 2000 push(1) push rn, rm / push rn load register to stack description the push instruction load one or two 16-bit data from general registers to software stack. in the instruction of ?push rn, rm?, there are some restrictions on rn and rm. - rn and rm should not be r15. - if rn is one of the 8 registers from r0 to r7, rm should also be one of them. if rn is one of the registers from r8 to r14, rm should also be one of them. for example, ?push r7, r8? is illegal. - if rn is the same as rm, push op eration occurs only once. ?push rn, rn? is equivalent to ?push rn?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 rm 1 1 1 1 0 rn operation if(rn == rm) { // push rn dm[sp] := rn sp := sp ? 2 } else { dm[sp] := rn dm[sp ? 2] := rm sp := sp ? 4 } exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 90 - mcu team lsi division system lsi business april 2000 push(2) push an, am / push an load register to stack description the push instruction load one or two 22- b it data to software stack from extended registers. in the instructi on of ?push an, am?, there ar e some restrictions on an and am. - an and am should not be a15. - if an is the same as am, push operation occurs only once. ?push an, an? is equivalent to ?push an?. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 0 1 am 1 1 1 1 1 an operation if(an == am) { // push an dm[sp] := rn dm[sp ? 2] := {10?h000, en} sp := sp ? 4 } else { dm[sp] := rn dm[sp ? 2] := {10?h000, en} dm[sp ? 4] := rm dm[sp ? 6] := {10?h000, em} sp := sp ? 8 } exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 91 - mcu team lsi division system lsi business april 2000 retd retd ret. from subroutine with delay slot description the retd (return from subroutine with dela y slot) instruction is used to finish a subroutine and return by jumping to the address specified by the link register or a14. the difference between retd and jmp a14 is that retd has a delay slot, which allows efficient implem entation of small subroutines. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 1 operation pc := a14 exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 92 - mcu team lsi division system lsi business april 2000 ret_fiq ret_fiq return from fast interrupt description the ret_fiq (return from fast interrupt) instruction is used to finish a fiq handler and resume the normal program execution. when this instruction is executed, ssr_fiq (saved sr) is restored into sr, and the program control transfers to (spch_fiq:spcl_fiq). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 0 operation sr := ssr_fiq pc := (spch_fiq:spcl_fiq) exceptions none. notes fast interrupt is requested through the core signal nfiq. when the request is acknowledged, sr and current pc are saved in the designated registers (namely ssr_fiq and spch_fiq:spcl_fiq) assigned for fiq processing. such bits in sr as fe, ie, and te are cleared, and pm is set.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 93 - mcu team lsi division system lsi business april 2000 ret_irq ret_irq return from interrupt description the ret_irq (return from interrupt) instruction is used to finish an irq handler and resume the normal program execution. when this instruction is executed, ssr_irq (saved sr) is restored into sr, and the program control transfers to (spch_irq:spcl_irq). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 0 1 operation sr := ssr_irq pc := (spch_irq:spcl_irq) exceptions none. notes interrupt is requested through the core signals nirq. when the request is acknowledged, sr and current pc are saved in the designated registers (namely ssr_irq and spch_fiq:spcl_irq) assigned for irq processing. such bits in sr as ie and te are cleared, and pm is set.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 94 - mcu team lsi division system lsi business april 2000 ret _ swi ret_swi return from software interrupt description the ret_swi (return from software interrupt) instruction is used to finish a swi handler and resume the normal program execution. when this instruction is executed, ssr_fiq (saved sr) is restored into sr, and the program control transfers to the address a14 (link register). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 operation sr := ssr_swi pc := a14 exceptions none. notes software interrupt is initiated by execu ting a swi instruction from applications. when swi instruction is executed, sr and current pc are saved in the designated registers (namely ssr_swi and a14) assigned for swi processing.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 95 - mcu team lsi division system lsi business april 2000 rl rl rn rotate left description the rl (rotate left) instruction rotates the value of rn left by one bit and stores the result back in rn. t bit is upda ted as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 1 1 1 1 0 rn operation rn := rn << 1, rn[0] = msb of rn before rotation t bit := msb of rn before rotation exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 96 - mcu team lsi division system lsi business april 2000 rr rr rn rotate right description the rr (rotate right) instruction rotates the value of rn right by one bit and stores the result back in rn. t bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 0 0 1 1 1 0 rn operation rn := rn >> 1, msb of rn = rn[0] before rotation t bit := rn[0] before rotation exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 97 - mcu team lsi division system lsi business april 2000 rrc rrc rn rotate right with carry description the rrc (rotate right with carry) instruction rotates the value of (rn:t bit) right by one bit and stores the result back in rn. t bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 0 1 1 1 0 rn operation rn := rn >> 1, msb of rn = t bit before rotation t bit := rn[0] before rotation exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 98 - mcu team lsi division system lsi business april 2000 sbc (1) sbc rn, ri subtract with carry register description the sbc (subtract with carry) instruction is used to synthesize 32-bit subtraction. if register pairs r0, r1 and r2, r3 hold 32-bit values (r0 and r2 hold the least- significant word), the following instructions leave the 32-bit result in r0, r1: sub r0, r2 sbc r1, r3 sbc subtracts the value of register ri, and the value of the carry flag (stored in the t bit), from the value of register rn, and stores the result in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 0 1 1 ri operation rn := rn + ~ri + t bit t bit := carry from (rn + ~ri + t bit) v flag := overflow from (rn + ~ri + t bit) if(rn == r6/r7) z0/z1 := ((rn + ~ri + t) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 99 - mcu team lsi division system lsi business april 2000 sbc (2) sbc rn, # subtract with carry immediate description the sbc (subtract with carry immediate) instruction is used to synthesize 32-bit subtraction with an immediat e operand. if register pair r0, r1 holds a 32-bit value (r0 holds the least-significant word), the following instructions leave the 32-bit subtraction result with 34157856h in r0, r1: sub r0, #7856h sbc r1, #3415h sbc subtracts the value of , and the value of the carry flag (stored in the t bit), from the value of rn, and stores the result in register rd. the t bit and the v flag are updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 1 1 1 1 1 rn operation rn := rn + ~ + t bit t bit := carry from (rn + ~ + t bit) v flag := overflow from (rn + ~ + t bit) if(rn == r6/r7) z0/z1 := ((rn + ~ + t) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 100 - mcu team lsi division system lsi business april 2000 setsr setsr bs:3 set sr description the setsr (set sr) instruction is used to set a specified bit in sr as follows: setsr fe / ie / te / v / z0 / z1 / pm to set the t bit, one can do as follows: cmp eq, r0, r0 to clear a specified bit in sr, the clrsr instruction (in page 45) is used. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 0 0 0 1 operation sr[] := 1 exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 101 - mcu team lsi division system lsi business april 2000 sr sr rn shift right description the sr (shift right) instruction shifts the value of rn right by one bit and stores the result back in rn. t bit is upda ted as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 0 1 1 1 0 rn operation rn := rn >> 1, with rn[15] set to 0 t bit := rn[0] before shifting exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 102 - mcu team lsi division system lsi business april 2000 sra sra rn shift right arithmetic description the sra (shift right arithmetic) instruction shifts the value of rn right by one bit and stores the result back in rn. while doing so, the original sign bit (most significant bit) is copied to the most signi ficant bit of the result. t bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 0 1 1 1 1 0 rn operation rn := rn >> 1, with rn[15] set to the original value t bit := rn[0] before shifting exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 103 - mcu team lsi division system lsi business april 2000 srb srb rn shift right byte description the srb (shift right byte) instruction shifts the value of rn right by 8 bit and stores the result back in rn. the high 8 bit positions are filled with 0?s. t bit is updated as a result of this operation. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 0 1 1 1 1 1 0 rn operation rn[7:0] := rn[15:8] and rn[15:8] := 8?h00 t bit := rn[7] before shifting exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 104 - mcu team lsi division system lsi business april 2000 sub (1) sub rn, ri subtract register description the sub (subtract register) instruction is used to subtract a 16-bit register value from another 16-bit register value. 32-bit subtraction can be achieved by executing sbc instruction in pair with this instruction (see page 98). sub subtracts the value of register ri from the value of rn, and stores the result in register rn. the t bit and the v flag are updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 0 0 1 ri operation rn := rn - ri t bit := carry from (rn - ri) v flag := overflow from (rn - ri) if(rn == r6/r7) z0/z1 := ((rn ? ri) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 105 - mcu team lsi division system lsi business april 2000 sub (2) sub rn, # subtract small immediate description this form of sub instruction is used to subtract a 7-bit immediate value from a register it subtracts the value of from th e value of register rn, and stores the result in register rn. the t bit and the v flag is updated based on the result. 15 14 13 12 11 8 7 6 0 0 0 0 0 rn 1 operation rn := rn - t bit := carry from (rn - ) v flag := overflow from (rn - ) if(rn == r6/r7) z0/z1 := ((rn - ) == 0) exceptions none. notes is an unsigned amount.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 106 - mcu team lsi division system lsi business april 2000 sub (3) sub an, ri subtract extended register description this form of sub instruction (subtract extended register) is used to add a 16-bit unsigned register value from a 22-bit value in register. this instruction subtracts the value of 16-bit register ri from the value of 22-bit register an, and stores th e result in register an. 15 14 13 12 11 10 8 7 6 5 4 3 0 1 0 1 0 1 an 1 1 0 0 ri operation an := an - ri exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 107 - mcu team lsi division system lsi business april 2000 sub (4) sub an, # subtract large immediate description the sub (subtract large imme diate) instruction is used to subtract a 16-bit unsigned immediate value from a 22-bit register. sub subtracts the value of from the value of an, and stores the result in register an. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 0 0 0 0 1 1 1 1 1 1 an operation an := an - exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 108 - mcu team lsi division system lsi business april 2000 sub (5) sub an, # subtract 5-bit immediate description this form of sub instruction (subtract extended register) is used to subtract a 5- bit unsigned immediate value from a 22-bit register. this instruction subtracts the value of 5-bit immediate from the value of 22-bit register an, and stores the result in register an. 15 14 13 12 11 10 8 7 6 5 4 0 1 0 1 0 1 an 0 1 1 operation an := an - exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 109 - mcu team lsi division system lsi business april 2000 swi swi # software interrupt description the swi (software interrupt) instruction performs a specified set of operations (i.e., an swi handler). this instruction can be used as an interface to the low-level system software such as operating system. executing this instruction is similar to performing a function call. however, interrupts (irq and trq) will be masked off so that when a software interrupt is handled, it can be seen as an uninterrup tible operation. note that fiq can still be triggered when an swi is serviced. return from a swi handler is done by ret_swi unlike normal function calls. 15 14 13 12 11 10 9 8 7 6 5 0 1 0 0 1 1 1 1 0 0 1 operation a14 := pc + 2 ssr_swi := sr ie := 0, te := 0 pc := << 2 exceptions none. notes program addresses from 000000h to 0000feh are reserved for swi handlers. swi vectors 0 and 1 are not used, as the addresses from 000000h to 000007h are reserved for other interrupts.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 110 - mcu team lsi division system lsi business april 2000 sys sys # system description the sys (system) instruction is used for system peripheral interfacing using da[4:0] and nsysid core signals. 15 14 13 12 11 10 9 8 7 6 5 4 0 1 0 0 1 1 1 1 0 0 0 1 operation core output signal da[4:0] := , da[21:5] := (unchanged) core output signal nsysid := low exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 111 - mcu team lsi division system lsi business april 2000 tst (1) tst rn, ri test register description the tst (tst register) instruction is used to determine if many bits of a register are all clear, or if at least on e bit of a register is set. tst performs a comparison by logically anding the value of register rn with the value of ri. t bit is set according to the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 1 1 1 ri operation temp := rn & ri t bit := ((rn & ri) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 112 - mcu team lsi division system lsi business april 2000 tst (2) tst r0, # test small immediate description this type of tst instruction is used to de termine if many bits of a register are all clear, or if at least one bit of a register is set. tst performs a comparison by logically anding the value of register rn with the value of ri. t bit is set according to the result. 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 0 1 1 operation temp n := rn & t bit := ((rn & )[7:0] == 0) exceptions none. notes the register used in this operation is fixed to r0. therefore, the operand should be placed in r0 before this instruction executes.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 113 - mcu team lsi division system lsi business april 2000 tst (3) tst rn, # test large immediate description this type of tst instruction is used to de termine if many bits of a register are all clear, or if at least one bit of a register is set. tst performs a comparison by logically anding the value of register rn with the value of ri. t bit is set according to the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 1 1 1 1 1 1 rn operation temp := rn & t bit := ((rn & ) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 114 - mcu team lsi division system lsi business april 2000 tstsr tstsr bs:3 test sr description the tstsr (test sr) instruction is used to test a specified bit in sr as the following example shows: tst fe / ie / te / v / z0 / z1 / pm to set or clear a specified bit, the setsr (in page 100) or clrsr (in page 45) instruction is used. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 1 0 0 1 1 1 1 0 1 0 0 1 0 operation t bit := ~sr[] exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 115 - mcu team lsi division system lsi business april 2000 xor (1) xor rn, ri xor register description the xor (xor register) instruction is us ed to perform bitw ise xor operation on two values in registers, rn and ri. the result is stored in register rn. the t bit is updated based on the result. 15 14 13 12 11 8 7 6 5 4 3 0 1 0 0 0 rn 0 1 1 0 ri operation rn = rn ^ ri t bit = ((rn ^ ri) == 0) if(rn == r6/r7) z0/z1 := ((rn^ri) == 0) exceptions none. notes none.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 116 - mcu team lsi division system lsi business april 2000 xor (2) xor r0, # xor small immediate description this type of xor instruction is used to perform bitwise xo r operation on two values in register r0 and . the result is stored in register r0. the t bit is updated based on the result. 15 14 13 12 11 10 9 8 7 0 1 0 0 1 1 0 1 0 operation r0 = r0 ^ t bit = ((r0 ^ )[7:0] == 0) exceptions none. notes the register used in this operation is fixed to r0. therefore, the operand should be placed in r0 before this instruction exec utes. is zero-extended to a 16-bit value before operation.
excellence in low-power the way mcu/dsp should be calmrisc16 reference manual - 117 - mcu team lsi division system lsi business april 2000 xor (3) xor rn, # xor large immediate description this type of xor instruction is used to perform bitwise xo r operation on two values in register rn and . the result is stored in register rn. the t bit is updated based on the result. 15 14 13 12 11 10 9 8 7 6 5 4 3 0 1 0 0 0 0 1 1 0 1 1 1 1 rn operation rn = rn ^ t bit = ((rn ^ ) == 0) if(rn == r6/r7) z0/z1 := ((rn^) == 0) exceptions none. notes this is a 2-word instruction, where the 16-bit immediate follows the instruction word shown above. unlike 1-word instru ctions, therefore, fetching of this instruction takes 2 cycles.
S5L840F (preliminary spec) clock & power management 6-1 5 clock & power management overview the clock & power management unit consists of cl ock control, power control and reset control. the clock control logic in S5L840F generates various sy stem clock signals: hclk_cp u for cpu, hclk for the ahb bus peripherals and pclk for the apb bus peripherals. the clock control logic allows bypassing of pll for slow clock and connection/disconnection of the clock to each peripheral block by software, which results in power reduction. also, S5L840F has the power control logic to support various power management schemes for optimal power consumption for a given application. the power m anagement provides five power modes: normal mode, slow mode, idle mode, standby mode and stop mode. in normal mode clock is supplied to cpu as well as all peripherals in S5L840F. the power consumption will be a maximum when all peripherals are turned on. also, user is allowed to control supply of the clock to peripherals by software. for example, if user does not need time r and dma, user can disconnect the clock to timer and dma to reduce the power consumption. the slow mode is a non-pll mode. only difference to normal mode is that the slow mode uses the external clock as a master clock in S5L840F rather than t he internal pll clock. in this case, the power consumed by pll itself is eliminated, and the power consumpt ion will depend on the frequency of the external clock. the idle mode disconnects the clock to cpu core while main taining the clock to all peripherals. by using this idle mode, we can further reduce t he power consumption by the cpu core. the wake-up from idle mode is done by an interrupt request to cpu. stop mode freezes all clocks to the cpu as well as peri pherals by disabling plls. the power consumption is only due to the leakage current in s3c2400, which is ua unit. the wake-up from stop mode can be done by activating external interrupt pins. the reset controller in s5h5002 consists of three re set types: hardware reset, software reset and watchdog reset. these types of reset are described in detail on page 6-9 reset controller . feature ? input frequency : 32.768 khz . ? output frequency range : 20mhz ? 100mhz. ? programmable frequency divider ? power management : normal, slow, idle, standby and stop. ? reset controller : hardware, software, and watchdog reset.
clock & power management S5L840F (preliminary spec) 6-2 function description clock generation figure 6-1 shows a block diagram of the clock generator. an external crystal clock is connected to the oscillation amplifier, and the pll (phase-locked-loop) converts t he low input frequency into a high-frequency clock required by S5L840F. the clock generator block also has a built-i n logic to stabilize the clock frequency after each system reset since the clock takes time before stabilized. maximum bus frequencies table 6-1 lists the maximum operating frequencies for t he S5L840F. when selecting strap settings, make sure that the bus divider ratios do not result in the bus frequencies that exceed these maximums. table 6-1. maximum bus frequencies internal bus maximum frequency module on the internal bus symbol ahb 100mhz cpu core, i/d cache, dma ,interrupt,clock & power, memory controller hclk apb 100mhz iic, gpio, uart, timer, rtc, iis, watchdog timer. pclk
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-3 pll0 pll0 osc stop mclk fine-tuner hclk_sel[1:0] mclk_sel[1:0] uclk_sel[1:0] 4-bit prescaler hclk ?? pclk ?? mclk uclk 0 1 2 3 0 1 2 3 0 1 2 3 4-bit prescaler pclk_div[3:0] pclk_div_on mclk_div[3:0] mclk_div_on 1'bx 1'bx 1'bx 0 1 tclk debug_region = debug_entry | debug_mode rclk figure 6-1. clock generator block diagram note until pllpms register is configured for desired clo ck frequency by user, osc clock (fin) is supplied to the system.
clock & power management S5L840F (preliminary spec) 6-4 pll (phase locked loop) the pll in the clock generator synchr onizes the output signal with the i nput reference signal in terms of frequency as well as phase. the output clock frequency fpllo is related to the reference input clock frequency fin by the following equation: fpllo = fin * (m + 1) / 2 (s+1) m = m (the value for divider m)+ 8, p = p(the value for divider p) + 2 change pll settings in normal operation mode during the operation of S5L840F in normal mode, if users want to change the frequency by modifying pms value, the pll lock time is automatica lly inserted. during the lock time, the clock will not be supplied to internal blocks in S5L840F. the timing diagram is as follow. pms setting pll lock time it changes to new pll clock after lock time automatically fpllo hclk figure 6-2. timing diagram of clock change in normal mode
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-5 power management all clock signals for each ahb and apb device can be maskabl e. the cpu controls each of the clocks to enable or disable it to perform local power management. the cpu itself have it?s own clock to be masked to enter idle mode which is one of the power saveing mode of S5L840F and can be woken up by interrupt. including idle power saving mode S5L840F provides 4 global power saving modes which are slow, idle, stanby, and stop. normal mode : all clocks are alive. slow mode : non-pll mode. unlike the normal mode, the slow mode uses an x-tal oscillator directly as hclk_cpu in the S5L840F without pll. in this mode, the power consumption depends on the frequency of the external clock only. the power consumption due to pll is excluded. this is mainly for the purpose of displaying time on the lcd screen while the mp3 player is not oper ating. to display the time the cpu needs to be engaged but it doesn?t need to run as fast as it runs to play audio. the cpu, rtc, and a number of peripherals are needed to run and display time on an lcd and they are required to operate with the x-tal frequency to consume minimun power. and all other pheriphrals that doesn?t need to operate are powered-down by hav ing their clocks masked. the x-tal frequency should be 32.768khz for the real time clo ck. to further reduce the power consumption in this case, the cpu may be in idle mode and woken-up , so to speak, at every 0.5sec to update the time display on the lcd while the rtc operates always. idle mode : the cpu can mask it?s own clock , hclk_cpu to enter idle mode and later interrupt input (nirq or nfiq) can wake the cpu up. before cpu enters idle mode it should guerantee there will be no further ahb+ transaction. the nirq and nfiq comes to the clock generation unit also to unmask hclk_cpu that enables the cpu to be woken-up and to recognize the interrupt consequently. stop mode : the x-tal osc is disabled to enter stop m ode. the external interrupt may cause return to normal mode. when it entered stop mode the s5l9260x mainta ins statically it?s late st state. the sdram(if exist) should be in self-refresh mode before entering st op mode. to support alarm function, real time clock(rtc) also should be able to wake up S5L840F from stop mode to normal mode. standby mode : at this power saving mode, just rtc and x-tal for rtc is operating and all others are powered-down. we can?t display time on the lcd bec ause the cpu and the lcd interface unit will be powered- down at this mode. but the time is correctly ma intained in the rtc and when woken up, the time can be displayed on the lcd. rtc operation with time di splay on an lcd requires rtc, cpu, buses and lcdif to be alive, so this is the case of slow power saving mode. to enter stop/standby mode follow the sequence : 1. if pclk == hclk / 2, make pclk is equal to hclk 2. calmadm3 sends the stop/standby power saving comm and to clock generation unit. the fsm in the clock generation unit excutes the following sequence (step 3~step6).
clock & power management S5L840F (preliminary spec) 6-6 3. masks all clocks. 4. changes clock source to x-tal osc from pll. 5. controls the pll to be disabled (power-down). 6. disable x-tal osc.(stop mode only) to recover to normal mode : ( initiated by external interrupt coming.) 1. external interrupt received. 2. upon receiving the external interrupt, the clock and reset generation unit asserts wresetn to ?low? that makes the x-tal osc to be enabled. 3. the clock and reset generation unit releases the wresetn to ?high? after 128 counts of the extint_cnt[6:0]. the wresetn is to reset the wdt(watch dog timer) and possibly released before the oscillator becomes stable. 4. the wdt counts the clock which is possibl y unstable and sends the clock generation unit the wdt_send signal that indicates the oscillator has been st ablized. all clocks are disbled until wdt_start is received . (except the clock for the wdt of cource which uses the clock hclk_pre that never be masked.) 5. the cpu enables the pll. 6. the cpu waits until the pll settles m onitoring the lock flag (?) of the pll. 7. changes the clock source to pll fr om x-tal osc. (the cpu changes it ?)
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-7 global power management : slow normal stop standby idle wresetn calmrisc32 sys instruction calmrisc32 sys instruction nfiq or nirq set pll_bypass clear pll_bypass sys_resetn (por) wresetn calmrisc32 sys instruction figure 6-5. the global power management
clock & power management S5L840F (preliminary spec) 6-8 local power management : while staying in normal mode t he cpu can mask each of the clocks for ahb and apb peripheral devices to expl oit power save as following : besides the global power saving mode stated above, we provide local power management scheme so that the cpu can disable each peripheral device by masking the clock to the device when it is not needed to operate. classification devices events no external events involved iis uart iic spi spdif lcd i/f adc rtc external events involved usb ms i/f smc i/f sd card i/f mmc card i/f usb connection card insertion card insertion card insertion card insertion
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-9 1. rtc power issues S5L840F does not provide a separate power and ground for rtc. 2. usb power management : the usb don?t have to operate when it?s not connected to usb cable. therefore the usb clocks can be masked after boot by cpu when it?s not used.. according to usb standard usb device goes to suspend st ate when there is no usb bus activity during more than 2.5us. S5L840F usb core sets d1 bit to ?1? when it comes to suspend state. usb power management register name bit cpu (clamrisc32) usb core description suspend_mode d1 r r/w this bit is set by the usb when it enters suspend mode uc_resume d2 r/w r the mcu sets this bit for a duration of 10ms to initiate a resume signaling usb_reset d3 r set the usb sets this bit if reset signaling is received from the host when usb cable is disconnected or there is no usb signal detected usb goes to suspend state. the cpu should check d1 bit periodically to recognize that usb goes to suspend state. then cpu controls to disable both of usb master clock and usb 48mhz clock. during the usb is in it?s suspend state, when usb signal from host is detected usb core generates interrupt. this interrupt is generated even when there is no clo ck supplied to usb core. the cpu recognizes the usb connection by the interrupt, enables usb clocks and sets t he bit d2 of the usb power management register to ?1?. then the usb changes it?s state to resume state.
clock & power management S5L840F (preliminary spec) 6-10 3. memory stick interface and smart media card interface power management : the memory stick interface and smart media card in terface unit may be powered- down when they don?t have cards in their slots. the following is a senario about how a card can be detected automatically in it?s slot. this is based on guess! when a card is inserted in it?s slot the external circuitry (with a circuit inside the card) might give a dc voltage level which is different to the level shown when the card is disconnected. this signal might be connected to external interrupt pin (or gpio ??) for cpu to recognize the card insertion. the cpu may enable the clocks for memory stick interfac e and smart media card interface each time when it needs to access the cards and disable the clocks after each access. the cpu might need to check the status of the card interface before disables the clock. (we need to check if there is any limit ation on when the clock can be disabled safely to be woken-up and work properly later time.) 4. sd card and multi-media card power management : the cpu polls the sc card interface to identify if a card is installed or not. if not installed it masks the clock for the sc card interface. when the cpu does not want to access the sc card it may mask the cl ock for the sc card interface. (is this correct ??)
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-11 reset controller the reset controller manages the various reset sources in the S5L840F. for a programmer, two reset control registers are provided: one used to invoke software rese t and one to read the status showing why the processor is reset after the reset sequence. after booting from t he reset, software can examine the reset status register (rstsr) to determine which types of reset has caused the reset condition. three types of reset in the S5L840F are described below: hardware reset hardware reset is invoked when the nreset pin is asse rted, and all units in the s5h5002 are initialized to a known state. hardware reset is intended to be used for pow er-up only. because the memory controller receives a full reset, all dynamic memory(dram/sdram) contents will be lost during hardware reset. the nreset_out pin is asserted during hardware reset. software reset software reset is invoked when the software reset (swr) bi t in the swrcon is set by software. after the swr bit is set, the S5L840F stays in reset state for 128 apb bus clocks (pclk) and then is allowed to boot again. the nreset_out pin is asserted during software reset watchdog reset watchdog reset is invoked when the watchdog enable bits in the wtcon[7:0] are set and the watchdog timer counter (wtcnt) overflows. the reset sequence of watchdog initiated reset is identical to software reset. when the wtcnt overflows, the S5L840F st ays in reset state for 128 apb bus clocks (pclk) and then is allowed to boot again. the nreset_out pin is asserted during watchdog reset.
clock & power management S5L840F (preliminary spec) 6-12 clock and power management special function registers pll pms value register (pllpms) fpllo = fin * (m+1) / 2 (s+1) table 6-3. recommended value of mdiv, sdiv m s fvco [mhz] fout [mhz] 5859 0 192.02048 96.01024 5859 1 192.02048 48.00512 5166 0 169.312256 84.656128 5166 1 169.312256 42.328064 5166 2 169.312256 21.164032 5511 0 180.617216 90.308608 5511 1 180.617216 45.154304 5511 2 180.617216 22.577152 5511 3 180.617216 11.288576 5512 0 180.649984 90.324992 5624 0 184.32 92.16 5624 1 184.32 46.08 5624 2 184.32 23.04 5999 0 196.608 98.304 5999 1 196.608 49.152 5999 2 196.608 24.576 5999 3 196.608 12.288 6201 0 203.227136 101.613568 6749 0 221.184 110.592 note: this value may be calculated using pllset.exe utility fr om samsung. this pll is not guaranteed that the pms
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-13 values are all zeros.
clock & power management S5L840F (preliminary spec) 6-14 clock control register (clkcon) register address r/w description reset value clkcon 0x3c50 0000 r/w clock control register 0x0000 0000 clkcon bit description initial state - [31:27] reserved 0 uclk_mask [26] 0 = uclk enable 1 = uclk disable 0 rclk_mask [25] 0 = rclk enable 1 = rclk disable 0 mclk_mask [24] 0 = mclk enable 1 = mclk disable 0 - [23] reserved 0 pclk_divon [22] 0 = prescaler off 1 = prescaler on 0 uclk_divon [21] 0 = prescaler off 1 = prescaler on 0 mclk_divon [20] 0 = prescaler off 1 = prescaler on 0 - [19:18] reserved 00 hclk_sel [17:16] 00 = osc 01 = pll0 10 = pll1 11 = not used 00 uclk_sel [15:14] 00 = osc 01 = pll0 10 = pll1 11 = not used 00 mclk_sel [13:12] 00 = osc 01 = pll0 10 = pll1 11 = not used 00 - [11:8] reserved 0000 uclk_div [7:4] 4-bit prescaler value uclk = input clock / (uclk_div + 1) when uclk_divon == 1 0000 mclk_div [3:0] 4-bit prescaler value mclk = input clock / (mclk_div + 1) when mclk_divon == 1 0000
S5L840F (preliminary spec) clock & power management 6-15 pll pms value register (pllpms) register address r/w description reset value pll0pms 0x3c50 0004 r/w pll pms value register undefined pll1pms 0x3c50 0008 r/w pll pms value register undefined pllpms bit description initial state reserved [31:30] reserved mdiv [29:16] main divider control undefined reserved [15:2] reserved sdiv [1:0] post-divider control undefined pll lock count register (plllcnt) register address r/w description reset value pll0lcnt 0x3c50_0014 r/w pll0 lock count register 0x0000 1fff pll1lcnt 0x3c50_0018 r/w pll1 lock count register 0x0000 1fff plllcnt bit description initial state reserved [31:13] reserved lock_cnt [12:0] pll lock count value (down counter) 0x1fff note: maximum pll locking time = 150 us pll lock status register (plllock) register address r/w description reset value plllock 0x3c50 0020 r pll lo ck status register 0 plllock bit description initial state reserved [31:2] reserved pll1_lock [1] pll1 lock status 0 : progress 1 : locking done 0 pll0_lock [0] pll0 lock status 0 : progress 1 : locking done 0
clock & power management S5L840F (preliminary spec) 6-16 pll control register (pllcon) register address r/w description reset value pllcon 0x3c50 0024 r/w pll control register 0 pllcon bit description initial state reserved [31:2] reserved pll1_pwd [1] pll1 power down 0 : pll1 is turned off. 1 : pll1 is turned on. 0 pll0_pwd [0] pll0 power down 0 : pll0 is turned off. 1 : pll0 is turned on. 0
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-17 clock power control register (pwrcon) register address r/w description reset value pwrcon 0x3c50_0028 r/w clock power control register 0x0020 4000 pwrcon bit description initial state - [31:15] reserved 0000 clk14 : gpio [14] 0 = disable 1 = enable 1 clk13 : timer [13] 0 = disable 1 = enable 0 clk12 : adc if [12] 0 = disable 1 = enable 0 clk11 : lcd if [11] 0 = disable 1 = enable 0 clk10 : rtc [10] 0 = disable 1 = enable 0 clk9 : iis [9] 0 = disable 1 = enable 0 clk8 : spdif [8] 0 = disable 1 = enable 0 clk7 : iic [7] 0 = disable 1 = enable 0 clk6 : spi [6] 0 = disable 1 = enable 0 clk5 : uart [5] 0 = disable 1 = enable 0 clk4 : sdc/mmc [4] 0 = disable 1 = enable 0 clk3 : memory stick [3] 0 = disable 1 = enable 0 clk2 : smc [2] 0 = disable 1 = enable 0 clk1 : usb [1] 0 = disable 1 = enable 0 clk0 : apbif [0] 0 = disable 1 = enable 0
clock & power management S5L840F (preliminary spec) 6-18 software reset control register (swrcon) the software reset control register has a software reset bit, which when set, causes a reset of the S5L840F. the software-reset bit (swr) is located within the least si gnificant bit of the write-only software reset register (swrcon). writing a one to this bit causes all on-chip resources to reset but does not cause the pll to go out of lock. the software reset bit is self-clearing. it is aut omatically cleared to zero afte r a few system clock cycles once it is set. writing zero to the software reset bit has no effect. care should be taken to restrict access to this register by programming mmu permissions. the following table shows the swrcon. register address r/w description reset value swrcon 0x3c50_0030 w software reset control register 0x0000 0000 swrcon bit description initial state swr [7:0] software reset. 1010_0101 = invoke a software reset of the chip. other value = do not invoke a software reset of the chip. this bit is self-clearing, and is automatically cleared several system clock cycles after it has been set. 0
s5h5002 risc microprocessor (preliminary spec) clock & power management 6-19 reset status register (rstsr) to determine the last cause or causes of the reset, the cp u can refer to the reset status register (rstsr). the S5L840F has three sources of reset: ? hardware reset ? software reset ? watchdog reset each rstsr status bit is set by a different source of reset, and can be cleared by setting a one of the other reset status bits. note that the hardware reset st ate of software and watchdog reset bit is zero. the table below shows the status bits within rstsr . register address r/w description reset value rstsr 0x3c50_0034 r/w reset status register 0x0000 0001 rstsr bit description initial state wdr [2] watchdog reset.(read only) 0 = watchdog reset has not occurred. 1 = watchdog reset has occurred this bit is cleared automatically when one of the other reset status bit is set. 0 swr [1] software reset.(read only) 0 = software reset has not occurred. 1 = software reset has occurred this bit is cleared automatically when one of the other reset status bit is set. 0 hwr [0] hardware reset.(read only) 0 = hardware reset has not occurred. 1 = hardware reset has occurred this bit is cleared automatically when one of the other reset status bit is set. 1
calmadm functional spec 40-1 calmadm3-0.2-030715 calmadm3 calmrisc16 and calmmac24 based audio dsp module with host capability functional specification 1.0 ver-030715 joongeon lee, optical player p/j
functional spec calmadm 40-2 revision history verion engineer date description 0.0 j.e.lee 2003-05-31 first version. copied & modified from calmadm2_spec_v01. 0.1 j.e.lee 2003-06-11 major changes from the last version: - added nfiq input pin - changed fast interrupt generation mechanism - added chapter 5, ?information for calmshine development? 1.0 j.e.lee 2003-07-15 major changes from the last version: - added sys_idle command - included bist modules - added riace flag in fiecfg of hfrs - added dbu output ports - fixed some errata green colored characters denote changes.
calmadm functional spec 40-3 table of contents 1 product overview 2 calmadm3 programming model 2-1 memory configuration 2-1-1 program memory 2-1-2 data memory 2-1-3 memory regions 2-1-4 mac area considerations 2-2 sequential data access 2-2-1 concepts and definitions 2-2-2 operations in linear mode 2-2-3 operations in ring mode 2-3 sfrs interface 2-4 calmadm3 internal controls 2-4-1 calmadm3 fast interrupt 2-4-2 calmadm3 sys commands 2-5 calmadm3 host function register set 3 calmadm3 hardware specifications 3-1 interface spec. 3-1-1 pin descriptions 3-1-2 pin timing diagrams 3-2 arbiter 3-3 ahbmiu (ahb master interface unit) 3-4 instruction cache 3-5 data caches 3-5-1 x-cache 3-5-2 x/y-cache as calm area data cache 3-6 sbfu (s-buffer unit) 3-7 sfrsi (sfrs interface unit) 4 constraints on using calmadm3 4-1 constraints on using calmrisc16f 4-2 constraints on using calmmac24f 4-3 constraints on accessing sequential buffers 4-4 constraints on accessing x/y-caches 4-5 definitions of abbreviations 5 information for calmshine development 5-1 simulator spec. 5-2 emulator spec.
functional spec calmadm 40-4 1 product overview introduction calmadm3, a calmrisc16 and calmmac24 based audio dsp module with host capability, is designed for high- quality audio processing and micro system control. it incl udes samsung's 16-bit mcu, calmrisc16, and 24-bit dsp, calmmac24. calmadm3 also includes three caches, one instruction cache and two data caches. to keep high performance with optimal die ar ea, two data caches are adopted instead of large on-chip data memories typically used in other audio processors. since it is used to encode/decode large audio data frames, calmadm3 includes two sequential buffers to handle input/output dat a efficiently. these sequential buffers can be act as a kind of ring buffer also. since calmadm3 is based on a 16-bit mcu, calmrisc16, but its target system bus, amba, is a 32-bit bus, calmadm3 cannot access slave r egisters on the system bus in usual way. in calmadm3, a specially designed slave register interface unit handles the 16-bit/32-bit data width conversion. in this document, we call calmadm3 as an abbreviation, adm . features calmrisc16f 16-bit low power & high performance risc micro-controller harvard style architecture: 4m byte program memory space, 4m byte data memory space 5-stage pipelined instruction execution 16-bit (half-word) instruction set sixteen 16-bit general-purpose registers with eight 6- bit extension registers ?f? denotes full scan version of calmrisc16 in this document, we call calmrisc16f as an abbreviation, calm . calmmac24f 24-bit (audword) high performance fixed-point d sp coprocessor for calmrisc16 micro-controller 1 cycle 24 24 mac operation 32k audword x data memory space & 32k audword y data memory space 2 multiplier accumulator registers, 4 general accumulator registers, and 8 pointer registers ?f? denotes full scan version of calmmac24 in this document, we call calmmac24f as an abbreviation, mac . *note: we defined 24-bit data unit of calmmac24f as aud-word in this document.
calmadm functional spec 40-5 internal memory instruction cache: 256 bit line, 4k byte, direct-mapped cache x data cache: 192 bit line, 6k byte, 2 way set associative cache y data cache: 192 bit line, 6k byte, 2 way set associative cache two 16-byte sequential buffers: configurable sequential ring buffer mode or sequential linear buffer mode ahb+ interface calmadm3 acts as an ahb+ master to access on/off-chip memories including memory mapped slave registers. sfrs interface converts 16-bit dual-access from calm to 32-bit bus access one-entry cache with auto- invalidation and auto-backup clock one ahb+ clock input performance calmrisc16f calmmac24f yc on/off-chip memories ahb+ arbiter & ahbmi sbf0 sbf1 dbu sfrs xc ic sfrsi ahb+ interface debug interface system interface scan interface bist interface calmrisc16f calmmac24f yc on/off-chip memories ahb+ arbiter & ahbmi sbf0 sbf1 dbu sfrs xc ic sfrsi ahb+ interface debug interface system interface scan interface bist interface figure 1-1. calmadm3 block diagram
functional spec calmadm 40-6 max. operating frequency = 100mhz @ (voltage: 1.65v ? 1.95v, temperature: -40 c ~ 125 c, process: samsung l18 2 calmadm3 programming model 2-1 memory configuration 000000h p0base 4m byte program memory (22 bit byte address) calm view 3fffffh 100000h 380000h p0size 512k byte p0 region 512k byte p1 region 512k byte p2 region 512k byte p7 region . . . 080000h 180000h p1base p1size p2base p2size p7base p7size system view 4g byte memory space (32 bit byte address) 000000h p0base 4m byte program memory (22 bit byte address) calm view 3fffffh 100000h 380000h p0size 512k byte p0 region 512k byte p1 region 512k byte p2 region 512k byte p7 region . . . 080000h 180000h p1base p1size p2base p2size p7base p7size system view 4g byte memory space (32 bit byte address) figure 2-1. program memory configuration
calmadm functional spec 40-7 2-1-1 program memory program memory configuration is show n in figure 2-1. 4m-byte cacheable instruction memory space is divided into 8 regions. calm accesses these regions through an in struction cache, i-cache. each region is individually mapped to 4g-byte system memory space as defined by it s base and size fields of its configuration register in hfrs. for example, if [20:18] bits of pa, the 21-bit pr ogram address bus from calm, equals ?000b?, it is in p0 region in calm view. pa[17:0] is converted as a byte address (multip lied by 2), added with p0base and mapped to 32-bit system memory space. before this address m apping, pa[17:0] is checked whether it is addressing the location beyond size limit defined by p0size. 2-1-2 data memory data memory configuration is shown in figure 2-2. 4m-b yte data memory space is divided into 8 memory regions and 2 register areas. each region is individually mapped to 4g-byte system memory space as defined by its base and size fields of its confi guration register in hfrs. calm regions lower 2m-byte area of 4m-byte data memory space is divided into 4 regions, accessed by calm only. calm accesses these regions through two data caches (x -cache and y-cache). as the cache for calm regions, 1m byte sfrs area 000000h 4m-byte data memory 16bit 3fffffh 200000h 128k byte mac x area 220000h 128k byte mac y area 300000h 512k byte calm3 region 256k byte hfrs area 256k byte sbl0 area 240000h 280000h 256k byte sbl1 area 2c0000h calm view 512k byte calm2 region 512k byte calm1 region 512k byte calm0 region 80000h 100000h 180000h c0base c0size c1base c1size c2base c2size c3base c3size ye unused xbase xsize*0.75 ybase ysize*0.75 s0base s0size s1base s1size yl yh xe unused xl xh mac view yh unused yl ye yh unused yl ye two 32k-audword data memory system view 4g-byte memory space (32-bit byte address) 4:3 data packing 4:3 data packing packed data packed data 32bit 128m byte sfrs area sfrsbase 1m byte sfrs area 000000h 4m-byte data memory 16bit 3fffffh 200000h 128k byte mac x area 220000h 128k byte mac y area 300000h 512k byte calm3 region 256k byte hfrs area 256k byte sbl0 area 240000h 280000h 256k byte sbl1 area 2c0000h calm view 512k byte calm2 region 512k byte calm1 region 512k byte calm0 region 80000h 100000h 180000h c0base c0size c1base c1size c2base c2size c3base c3size ye unused xbase xsize*0.75 ybase ysize*0.75 s0base s0size s1base s1size yl yh xe unused xl xh mac view yh unused yl ye yh unused yl ye two 32k-audword data memory system view 4g-byte memory space (32-bit byte address) 4:3 data packing 4:3 data packing packed data packed data 32bit 128m byte sfrs area sfrsbase figure 2-2. data memory configuration
functional spec calmadm 40-8 these two data caches operate similar to a two way set associative cache. if [21:19] bits of da, the 22-bit data address bus from ca lm, equals ?000b?, it is in c0 region in calm view. da[18:0] is added with c0base and mappe d to 32-bit system memory space. before this address mapping da[18:0] is checked whether it is addressing the location beyond size limit defined by c0size. mac regions mac x and mac y are dual memory for dual load capability of mac. each is 32k-audword. both of calm and mac can access these two regions. when da[21:17] equals ?10000b?, calm accesses x region. to access this region, calm uses x-cache as data cache. da[16:0] from calm is converted as x region a ddress before get into x-cac he. when da[21:17] is 10001b, calm accesses y region. to access this region, calm uses y-cache as data cache. da[16:0] from calm is converted as y region address before get into y-cache. mac accesses two mac areas with its two 15-bit audword data addresses, xa and ya. xa and ya are 2-bit left shifted (conversion to byte address) before get into the caches. the 6k-byte x-cache covers 32k-audword ma c x region. the 6k-byte y-cache covers 32k-audword mac y region. the addresses from x-cache and y-cache are convert ed as 4:3 reduction, added with xbase/ybase and mapped to 32-bit system memory space. before this address mapping the addresses are checked whether they are addressing the location beyond si ze limit defined by xsize/ysize. two words in highest address of mac x and two words in highest address of mac y are reserved for accessing sequential block areas. sbl0/sbl1 regions sequential block regions are used mainly for i nput and output of audio stream data frames. calm can access these regions randomly but mac can ac cess them in sequential way only. since these regions are out of mac?s memory space, mac cannot access these randomly. in adm, a special logic was added so that mac can access these regions sequentially. when da[21:18] is 1001b, calm ac cesses sbl0 area. da[17:0] is adde d with s0base and mapped to 32-bit system memory address. before this address mapping da[ 17:0] is checked whether it is addressing the location beyond size limit defined by s0size. when da[21:18] is 1010b, calm accesses sbl1 area similarly to sbl0 area. since adm has no caches for these areas, calm ac cesses system memory directly when it accesses these areas. when xa or ya are 7ffeh, mac accesses sb l0 area sequentially. when xa or ya are 7fffh, mac accesses sbl1 area sequentially. the sequential access es are modulated with the size limit. therefore, sequential accesses do not cause the size limit violation. more of sequential data accessing is described in later of this document. hfrs area hfrs (host function register set) area is reserved for memory-mapped registers of adm. hfrs area resides 2c0000h to 2fffffh address space in calm?s data memory space. registers in hfrs can be accessed by adm only. outside of adm cannot access these. sfrs areas sfrs (special function register set) area is reserved for system level memory-mapped registers. sfrs area is divided into two areas, psfrs area for slave registers in apb ips and hsfrs ar ea for slave registers in ahb ips. psfrs area resides 380000h to 3fffffh address space in calm?s data memory space. 512k-byte psfrs area is divided into 64 8k-byte blocks a nd mapped to 64m-byte system memory space. adm can handle up to 64 apb
calmadm functional spec 40-9 ips that have up to 8k-byte slave register set. hsfrs area resides 300000h to 37ffffh address space in calm?s data memory space. 512k-byte hsfrs area is divided into 32 16k-byte blocks and mapped to 64m-byte system memory space. adm can handle up to 32 ahb ips that have up to 16k-byte slave register set. me mory map and address translation of sfrs are shown in fig.2-3 and fig.2-4. 2-1-3 memory regions in adm are 16 memory regions. the regions are assigned as fig.2-5. each region has corresponding region control registers and flag in hfrs. the region control is performed by hardware in adm based on a region enable flag of recfg r egister and base address field and region size field of region configuration register in hfrs. because the base addre ss field is 24-bit corresponding to [31:8] bit location of 32-bit physical memory address, each region can be aligned 256-byte step boundaries in physical memory . . . . . . 300000h 3fffffh 380000h 1m byte logical srfs area hsfrs 512k byte psfrs 512k byte 16k byte 16k byte 16k byte 2m 64 ? 8k byte 8k byte 8k byte 16k byte 128m byte physical sfrs area hsfrsbase 16k byte 1m psfrsbase 32 ? sfrs (apb) 64m byte sfrs (ahb) 64m byte . . . 16k byte . . . 8k byte 8k byte 8k byte 4g byte memory space address translation (simple stuffing) . . . . . . 300000h 3fffffh 380000h 1m byte logical srfs area hsfrs 512k byte psfrs 512k byte 16k byte 16k byte 16k byte 2m 64 ? 8k byte 8k byte 8k byte 16k byte 128m byte physical sfrs area hsfrsbase 16k byte 1m psfrsbase 32 ? sfrs (apb) 64m byte sfrs (ahb) 64m byte . . . 16k byte . . . 8k byte 8k byte 8k byte 4g byte memory space address translation (simple stuffing) figure 2-3. sfrs memory map [21:19] = 111 [18:13] [12:0] [31:26] = psfrsbase [25:20] [12:0] [19:13] = 0 [21:19] = 110 [18:14] [13:0] [31:26] = hsfrsbase [25:21] [13:0] [20:14] = 0 base concatenation zero stuffing sfrs(apb) case sfrs(ahb) case physical address calm address [21:19] = 111 [18:13] [12:0] [31:26] = psfrsbase [25:20] [12:0] [19:13] = 0 [21:19] = 110 [18:14] [13:0] [31:26] = hsfrsbase [25:21] [13:0] [20:14] = 0 base concatenation zero stuffing sfrs(apb) case sfrs(ahb) case physical address calm address figure 2-4. sfrs address translation
functional spec calmadm 40-10 map. the size fields are defined as fig.2-6. when calm or mac issues a memory access, adm checks if the accessed region is enabled and if the accessed location is in valid region area defined by size field. if one of these two checks results false, adm issues an exception to calm instead of issuing the physical memo ry access. before adm issu es the physical memory access, it performs an address transl ation by adding base field to the logica l address issued from processors. 2-1-4 mac area considerations *note: this section is exactly same as the one in calmad m2 specification. if you are familiar with calmadm2, you don?t need to read this section. the target host of adm is 32-bit machine, mac is a 24-bit dsp and calm is a 16-bit risc processor. because of different size of unit data among three processors, fo llowing two address conversions are needed for mac x/y areas. da conversion for mac area because of the data unit difference, calm and mac have different address maps of ma c x/y area. (look at the structure difference of mac x/y area between calm view an d mac view in figure2-2) because of the difference, proper address conversion is needed when calm accesses mac x/y area. da[21:0] from calm is converted to da_mem[21:0] in following manner before it goes to caches or system memory. *da to da_mem conversion: if ((da[21:17] == 0b10000) or (da[21:17] == 0b10001)) da_mem[21:0] = ?da[21: 17],da[15:1],~da[16],da[0]? r15 s1 r14 s0 r13 y r12 x r11:r8 c3:c0 r7:r0 p7:p0 r15 s1 r14 s0 r13 y r12 x r11:r8 c3:c0 r7:r0 p7:p0 figure 2-5. region assignment r0~r11 1kb 2kb 4kb 8kb 16kb 32kb 64kb 128kb 256kb 512kb 512kb size code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 others r12,r13 (x,y) 1kb 2kb 4kb 8kb 16kb 32kb 64kb 128kb 128kb 128kb 128kb size r14,r15 (s0,s1) 1kb 2kb 4kb 8kb 16kb 32kb 64kb 128kb 256kb 256kb 256kb 0.75kb 1.5kb 3kb 6kb 12kb 24kb 48kb 96kb 96kb 96kb 96kb logical physical r0~r11 1kb 2kb 4kb 8kb 16kb 32kb 64kb 128kb 256kb 512kb 512kb size code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 others r12,r13 (x,y) 1kb 2kb 4kb 8kb 16kb 32kb 64kb 128kb 128kb 128kb 128kb size r14,r15 (s0,s1) 1kb 2kb 4kb 8kb 16kb 32kb 64kb 128kb 256kb 256kb 256kb 0.75kb 1.5kb 3kb 6kb 12kb 24kb 48kb 96kb 96kb 96kb 96kb logical physical figure 2-6. region size definitions
calmadm functional spec 40-11 calmmac24f sbf0 sbl0 area 4m byte data memory sbl1 area 240000h 280000h sbl0off sbl0 sbl1 0 1 2 3 sbf1 sbl1off 0 1 2 3 calmmac24f sbf0 sbl0 area 4m byte data memory sbl1 area 240000h 280000h sbl0off sbl0 sbl1 0 1 2 3 sbf1 sbl1off 0 1 2 3 figure 2-6. sequential access data flow else da_mem[21:0] = da[21:0] 4:3 reduction for unused bytes since mac is a 24-bit dsp and its memory data are word ( 32-bit) aligned, there are not -used bytes in data words of mac x/y area. since there is no physical memory for these bytes, two things should be considered. the one is accessing these bytes by calm. calm may acce ss these not-used bytes, but a write to these bytes cannot be done and a read from these bytes always results 00h. the second is waste of system memory area. if mac x/y ar eas are mapped to system memory directly, it causes waste 1/4 of system memory area. therefore, in adm, addresses of mac x/y area from x/y-caches are converted as 4:3 reduction before mapped to system memory addresses. as a re sult of this conversion, size of each mac x area and mac y area will be 96k-bytes in system memory instead of 128k-bytes. 2-2 sequential data access *note: this section is exactly same as the one in calmad m2 specification. if you are familiar with calmadm2, you don?t need to read this section. if a data block in the system memory is well-aligned and well-known stream data, it can be accessed in sequential. in adm, user can define two sequential blocks in calm data memory area and can access them sequentially through sequential buffers. there are tw o sequential access modes, linear mode and ring mode.
functional spec calmadm 40-12 2-2-1 concepts and definitions sequential block areas - data memory area in which sequential blocks can be defined. - in calm data memory area, two 256k-byte sequent ial block areas are defined. one starts from 240000h address and the other starts from 280000h. - calm can access these areas randomly but mac can?t access in normal way because these areas are defined out of mac x/y areas. adm offers special way for mac to access these areas sequentially. sequential blocks - well-aligned data memory area that can be se quentially accessed by mac through sequential buffers. - unit data in a sequential block can be word or hal f-word. however, a sequential block should be word aligned for efficient system memory access. - data in a sequential block are addressed with offset register. - these blocks are dynamic blocks that ca n be created, used and removed by software. - in linear mode, the size and boundary of a sequ ential block are implicitly defined by how user program accesses the sequential block. in ring mode , the size and boundary of a sequential block are explicitly defined by the values of begi n offset register and end offset register. sequential buffers - a kind of fifo that is used as buffer memory for mac to access sequential blocks sequentially. - these buffers can be both read buffer and write buffer. - pre-loading and post-storing capability are supported. these capabilities can be done explicitly by givi ng special command into control registers. - size of sequential buffers ? 128-bits ? 4 data for word data, 8 data for half-word data - address of sequential buffers ? sequential buffers are defined as a me mory data located in special address. ? sbf0 : 21fff8h (in x area) or 23fff8h (in y area) ? sbf1 : 21fffch (in x area) or 23fffch (in y area) sequential block offset registers - 18-bit registers that contain o ffset address of memory data to be accessed at next sequential access.
calmadm functional spec 40-13 - offset registers are automatically in creased just after a sequential access. - in ring mode, incremented offset register is com pared with the end offset register. if two register values are same, an offset register is set as the value of the begin offset register. - offset registers can be read or written directly since these are memory mapped in i/o area of calm. - when offset register is written, the value can be any address in sequential block area. the written value is independent from the values of the boundary-offset registers even in ring mode. - the bases of offsets are start add resses of sequential block areas. - the offset values are byte-address. sequential block boundary offset registers - 18-bit registers that contain boundary offset valu es (begin/end) of a sequential block used in ring mode. - in ring mode, a sequential block is define as below: begin offset =< sbl < end offset caution: end offset is not included in sequential block. - in linear mode, boundary offsets are not used. - these registers can be read or written directly si nce these are memory mapped in i/o area of calm. - the bases of boundary offsets are start addresses of sequential block areas. - the boundary-offset values are byte-address. ring mode vs. linear mode - in linear mode, the size and boundary of a sequentia l block is not fixed. defining a sequential block and checking its boundary totally depend on user program. - in ring mode, the size and boundary of a sequential block is defined by the values of begin offset register and end offset register. boun dary checking is performed by hardware. - in ring mode, when the offset register is increa se to meet the value of end offset register, two operations are automatically performed by hardware. 1. offset wrapping the offset register is set as the value of begin offset register. (we call it ?wrapping? in this document) 2. interrupt corresponding interrupt flag is set an d interrupt is forced to calm if the interrupt is enabled. 2-2-2 operations in linear mode following tables show how to access sbl0 in linear mode. sbl1 can be accessed similarly.
functional spec calmadm 40-14 table 2-1. sbl0 as a sequential read block in linear mode explicit operations implicit operations set sbl0off - set sbl0off as start offset of sequential block - invalidate all data words in sbf0 run buffer fill command - fetch words located from {sbl0off[ 17:4],sbl0off[3:2],00} to {sbl0off[17:4],11,00} in sbl0 into sbf0 - validate fetched words in sbf0 read sbf0 - data read - invalidate read word and increase sbl0off - if sbf0 is empty - fetch new 4 words in (sbl0off[17:4],0000b) location of sbl0 repeating read from sbf0 results sequential reads table 2-2. sbl0 as a sequential write block in linear mode explicit operations implicit operations set sbl0off - set sbl0off as start offset of sequential block - invalidate all data words in sbf0 write to sbf0 - data write - validate written word and increase sbl0off - if sbf0 is full - flush valid words in sbf0 into (sbl0off[17:4]-1,0000b) location of sbl0 and invalidate flushed words. repeating write into sbf0 results sequential writes run buffer flush command flush valid words and invalidate flushed words table 2-3. sbl0 area as randomly accessed data memory explicit operations implicit operations calm accesses sbl0 area in system memory directly to keep data consistency, - adm checks if it is hit on one-lined-cache (scache0) (scache0 consists of sbl0off as tag and sbf0 as a data line.) - write policy: write-through - no replacement is done on miss 2-2-3 operations in ring mode following tables show how to access sbl0 in ring mode. sbl1 can be accessed similarly.
calmadm functional spec 40-15 table 2-4. sbl0 as a sequential read block in ring mode explicit operations implicit operations set sbl0begin and sbl0end * no special implicit operations set sbl0off run buffer fill command * same as descriptions in table2-1 read sbf0 - data read - invalidate read word and increase sbl0off - if sbl0off is equal to sbl0end, - set sbf0 interrupt flag - invalidate entire sbf0 - set sbl0off as sbl0begin - fetch words located from {sbl0off[17:4],sbl0off[3:2],00} to {sbl0off[17:4],11,00} in sbl0 into sbf0 - validate fetched words in sbf0 - if sbf0 is empty - fetch new 4 words from (sbl0off[17:4],0000b) location of sbl0 repeating read from sbf0 results sequential reads in ring mode table 2-5. sbl0 as a sequential write block in ring mode explicit operations implicit operations set sbl0begin and sbl0end * no special implicit operations set sbl0off * same as descriptions in table2-2 write to sbf0 - data write - validate written word and increase sbl0off - if sbl0off is equal to sbl0end, - set sbf0 interrupt flag - flush valid words and invalidate flushed words - set sbl0off as sbl0begin - if sbf0 is full - flush valid words in sbf0 into (sbl0off[17:4]-1,0000b) location of sbl0 and invalidate flushed words. repeating write into sbf0 results sequential writes run buffer flush command * same as descriptions in table2-2 in ring mode, calm randomly accesses sbl0 area in the same way as the case of linear mode. refer table2-3.
functional spec calmadm 40-16 write valid read valid stand-by first read sfrs ? calm sfrs ? sfrbuf first write calm ? sfrbuf second read sfrbuf ? calm second write sfrbuf ? sfrs calm ? sfrs 16-bit read 16-bit read hit 16-bit read miss 16-bit write 16-bit write hit 16-bit write miss backup sfrbuf push sfrbuf recover sfrbuf pop sfrbuf exception recover command 16-bit read 16-bit write notes -8-bit write ? no operation - 8-bit read ? dummy read, fixed to reading zero - after backup ? stand-by state -after recover ? recovered state according to the recovered state flags write valid write valid read valid read valid stand-by stand-by first read sfrs ? calm sfrs ? sfrbuf first write calm ? sfrbuf second read sfrbuf ? calm second write sfrbuf ? sfrs calm ? sfrs 16-bit read 16-bit read hit 16-bit read miss 16-bit write 16-bit write hit 16-bit write miss backup sfrbuf push sfrbuf recover sfrbuf pop sfrbuf exception recover command 16-bit read 16-bit write notes -8-bit write ? no operation - 8-bit read ? dummy read, fixed to reading zero - after backup ? stand-by state -after recover ? recovered state according to the recovered state flags figure 2-7. sfrsi state & function diagram 2-3 sfrs interface since adm works as a host processor of 32-bit amba bus based system, adm should read and write 32-bit sfrs registers in the ips on the 32-bit amba buses. be cause adm is based on a 16-bit mcu, calmrisc16, it cannot access sfrs registers in usual way. in adm, a specially designed slave register interface unit, sfrsi, handles the 16-bit/32-bit data width conversion. to access a 32-bit register, calm accesses the register twic e. one is for higher half of the register. the other is for lower half of the register. we call this accessing twice as dual-access (dual-read, dual-write). main function of sfrsi is conversion of dual-access from calm to one 32-bit access to amba bus. to perform this conversion, sfrsi is designed as an o ne-entry cache composed with a 16-bit data register, an address register tagged to the data, a valid flag and a read/write mode flag. in addition to the one-entry cache function, sfrsi performs two special functions. one is auto-invalidation on hit. it guar antees that adm converts two 16-bit calm accesses to one 32-bit bus access. without this auto-invalidation, 3 or more calm accesses may cause only 1 bus access when calm repeats accessing same sfrs register. the other one is auto-backup on exception. since dual-access is a single access to a sf rs register, it is an atomic operation. however, an exception (interrupt) may occur during calm performs a dual-access. it may separate an atomic operation into two operations and may cause a failure on system operation. to prevent the separation of atomic dual-access, the contents of one-entry cache in sfrsi should be backup on exception so that they can be recovered before returning from the exception handling routine. in adm, the backup on exception is done automatically by sfrsi hardware and the recovery is done on special command. we defined one of sys commands of calm as the recovery command so that the system programmers can insert the command into the end of exception handling routines. fig.2-7 shows the operation of sfrsi. when reading a sfrs register, dual-read is not mandator y. calm can read any sfrs register freely in 16-bit mode. when writing, dual-write is mandatory. calm can wr ite any sfrs register in 16-bit mode, but only when the write hit occurs, the sfrs register is physically writt en. the sfr buffer data written by calm is written to the
calmadm functional spec 40-17 sfrs register if next sfrs access results write hit. t he data is discarded if the next sfrs access is read or write-miss. 2-4 calmadm3 internal controls 2-4-1 calmadm3 fast interrupt adm has two fast interrupt signals. one is nfiq, one of ad m input pins. the other is internal fast interrupt signal. when one or two of these are active, fast interrupt request is issued to calm. internal fiqs in adm are four sources of internal fast interrupt. these sources are defined as interrupt pending flags of admstat register in hfrs. two of them, s0wif and s1 wif, are wrapping interrupt flags set by sequential buffer unit described in section 2-2-1. remaining two of them, priaif and driaif, are results of region check described in section 2-1-3. when one or more of 8 program region checks failed, priaif is set. when one or more of 8 data region checks failed, driaif is set. user can enable/disable each interrupt source by set/ resetting corresponding interrupt enable flag of fiqcfg in hfrs. if one or more among enabled interrupt pending flags are set, the internal fast interrupt signal is active. user should clear the interrupt pending fl ag by writing 1 into that flag before returning from the corresponding interrupt service routine. 2-4-2 calmadm3 sys commands in adm, two sys commands are used internally. sys #5h is defined as ?sys_idle? meaning t hat calm goes to idle mode after ex ecution of this command. note that, before ?sys_idle? is issued, ?ready_clk_down? flag in ad mstat register should checke d if it?s on. upon the interrupts or wake up command from debugger unit, calm exits from idle mode. sys #18h is defined as ?sys_rsfrb? meaning recove ry of sfr buffer descr ibed in section 2-3. 2-5 calmadm3 host function register set address base the address values below are 7bit off set values. the fu ll address values are additions of the offsets and the base address.
functional spec calmadm 40-18 base address of adm function register set: 2c0000h register set 1: config admcfg: adm configuration register reset value : 0000h base + 0h mode : read/write bit name description 15 sbf0 mode [3] sequential access mode selection bit 0 : linear mode 1 : ring mode 14:12 sbf0 mode [2:0] * when sbf0 mode [2] is 0, access uni t of external memory is 32 bit. * when sbf0 mode [2] is 1, access uni t of external memory is 16 bit. 00x : mac input[23:0] <-- external input[23:0] 01x : mac input[23:0] <-- external input[32:8] 100 : mac input[23:0] <-- zero exte nsion of external input[15:0] 101 : mac input[23:0] <-- sign ext ension of external input[15:0] 11x : mac input[23:8] <-- external input[15:0], mac input[7:0] <-- 00h 000 : external output[31:0] <-- zero extension of mac output[23:0] 001 : external output[31:0] <-- sign extension of mac output[23:0] 01x : external output[31:8] <-- mac out put[23:0], external output[7:0] <-- 00h 10x : external output[15:0] <-- mac_output[15:0] 11x : external output[15: 0] <-- mac_output[23:8] 11:8 sbf1 mode [3:0] * similar to the description of ?sbf0 mode [3:0]? 7:6 - not used (reading returns zero) 5:4 xyrr xy-cache round robin code. when a calm area access is cache-missed, one of x- or y-cache is replaced according to this code. 00: x- and y-cache are selected one after another (round robin). at the first miss, x-cache is selected. 01: x-cache is selected. 1x: y-cache is selected. 3:1 - not used (reading returns zero) 0 ldcinv this flag is for partial invalidation. if it is set, all ldc instruction of calm invalidates the target address line in i-cache. * note: when sbf0mode/sbf1mode flags are written, newly updated values are not effective to the operation of sequential buffers. new values are effective after the s equential buffer is newly initialized, which means that sbl0off/sbl1off registers are newly written. * note: xyrr bits should change while both x- and y-caches are disabled. otherwise, data coherence may corrupt.
calmadm functional spec 40-19 fiecfg: fast interrupt enable/disable confi guration register reset value : 0000h base + 2h mode : read/write bit name description 15:9 - not used (reading returns zero) 8 riace region invalid access check enable 0 : region check disable, 1 : region check enable 7:4 - not used (reading returns zero) 3 driaie data region invalid ac cess interrupt enable 0 : interrupt disable, 1 : interrupt enable 2 priaie program region invalid access interrupt enable 0 : interrupt disable, 1 : interrupt enable 1 s1wie sequential buffer 1 wrapping interrupt enable 0 : interrupt disable, 1 : interrupt enable 0 s0wie sequential buffer 0 wrapping interrupt enable 0 : interrupt disable, 1 : interrupt enable * note: enabling ?region invalid access check? may cause performance degradation of adm in terms of both speed and power. you can set riace flag only in debug mode, and re set it in normal operation mode that needs the full performance of adm. recfg: region enable/disabl e configuration register reset value : 0001h base + 4h mode : read/write bit name description 15:0 re 0 : region disable, 1 : region enable * note: re[0] is reset as high (enabled) becau se region0 contains boot code(reset vector). r0cfg_h/l: region0 base & size configuration register reset value : 0000h_0002h base + 6h mode : read/write bit name description
functional spec calmadm 40-20 [15:0] base[23:8] base address of region0 in physical memory space. mapped to [31:16] of physical memory address. base + 8h mode : read/write bit name description [15:8] base[7:0] base address of region0 in physical memory space. mapped to [15:8] of physical memory address. [7:4] - not used (reading returns zero) [3:0] size size code of region 0. 0000: 1k-byte 0001: 2k-byte 0010: 4k-byte 0011: 8k-byte 0100: 16k-byte 0101: 32k-byte 0110: 64k-byte 0111: 128k-byte 1000: 256k-byte 1001: 512k-byte others: 512k-byte r1cfg_h/l ~ r15cfg_h/l: region1~15 base & size configuration register reset value: xxxx_xxxxh base + ah, eh, ?, 42h mode : read/write bit name description [15:0] base[23:8] base address of region1~15 in physica l memory space. mapped to [31:16] of physical memory address. base + ch, 12h, ?, 44h mode : read/write bit name description [15:8] base[7:0] base address of region1~15 in physica l memory space. mapped to [15:8] of physical memory address. [7:4] - not used (reading returns zero) [3:0] size size code of region 0. *code definition is same as size definition of r0cfg
calmadm functional spec 40-21 sfrscfg: sfrs area base configuration register reset value : xxxxh base + 46h mode : read/write bit name description [15:10] psfrsbase base address of sfrs(apb) area in physical memory space. mapped to [31:26] of physical memory address. [9:8] - not used (reading returns zero) [7:2] hsfrsbase base address of sfrs(ahb) area in physical memory space. mapped to [31:26] of physical memory address. [1:0] - not used (reading returns zero) register set 2: control registers cachecon: cache control register reset value : 0333h base + 48h mode : write only. reading returns zero. bit name description [15:10] - not used (reading returns zero) [9:8] ic command flag 00: no operation 01: i-cache invalidation 10: i-cache enable. 11: i-cache disable (go to bypass mode). [7] - not used (reading returns zero) [6:4] xc command flag 000: no operation 001: x-cache invalidation 010: x-cache enable. 011: x-cache disable (go to bypass mode). 1xx: x-cache flush [3] - not used (reading returns zero) [2:0] yc command flag * similar to the description of ?xc command flag? sbfcon: sequential buffer control register reset value : 0000h base + 4ah mode : write only. reading returns zero. bit name description [15:14] - not used (reading returns zero)
functional spec calmadm 40-22 [13:12] sbf0 command flag 00,11: no operation 01: buffer fill command 10: buffer flush command [11:10] - not used (reading returns zero) [9:8] sbf1 command flag * similar to the description of ?sbf0 command flag? [7:0] - not used (reading returns zero) register set 3: state registers admstat: adm state register reset value : 0100h base + 4ch mode : read/write bit name description 15:9 - not used (reading returns zero) 8 ready_clk_down read only. writing does not affect this flag. 0: sub-blocks in adm are running 1: sub-blocks in adm are ready to accept ?no clock?. this flag is reset as zero when one or more of adm sub-blocks are doing at least one pending action like external memory access. adm should check if this flag is set before it issues system idle or software reset. 7:4 - not used (reading returns zero) 3 driaif data region invalid access interrupt flag 0 : interrupt not issued, 1 : interrupt issued 2 priaif program region invalid access interrupt flag 0 : interrupt not issued, 1 : interrupt issued 1 s1wif sequential buffer 1 wrapping interrupt flag 0 : interrupt not issued, 1 : interrupt issued 0 s0wif sequential buffer 0 wrapping interrupt flag 0 : interrupt not issued, 1 : interrupt issued * note: you can clear a specific bit of interrupt flags by wr iting a data to this register. it clears only the bit positions corresponding to those set to one in the written data. the bit positions corresponding to those that are set to zero in the written data remains as they are. cachestat: cache status register reset value : 0000h
calmadm functional spec 40-23 base + 4eh mode : read only. writing does not affect this register. bit name description [15:10] - not used (reading returns zero) [9:8] ic state flag 00: undefined 01: i-cache is in invalidation state. 10: i-cache is in normal state. 11: i-cache is in bypass state. [7] - not used (reading returns zero) [6:4] xc state flag 000: undefined 001: x-cache is in invalidation state. 010: x-cache is in normal state. 011: x-cache is in bypass state. 1xx: x-cache is in flush state. [3] - not used (reading returns zero) [2:0] yc state flag * similar to the description of ?xc command flag? sbfstat: sequential buffer status register reset value : 0000h base + 50h mode : read only. writing does not affect this register. bit name description [15] - not used (reading returns zero) [14:12] sbf0 state flag 000: sequential buffer 0 is in non-sequential access mode 001: sequential buffer 0 is being filled 010: sequential buffer 0 is being flushed 100: sequential buffer 0 is in initialized mode 101: sequential buffer 0 is in sequential read mode 110: sequential buffer 0 is in sequential write mode others: undefined [11] - not used (reading returns zero) [10:8] sbf1 state flag * similar to the description of ?sbf0 state flag? [7:0] - not used (reading returns zero) register set 4: sequential buffer function registers sbl0off_h: higher bits of offset register of sequential block 0 area reset value : 0000h base + 52h mode : read/write
functional spec calmadm 40-24 bit name description [15:2] - not used (reading returns zero) [1:0] sbl0off_h higher 2 bits of 18-bit sequential block 0 offset (sbl0off[17:16]) sbl0off_l: lower bits of offset register of sequential block 0 area reset value : 0000h base + 54h mode : read/write bit name description [15:2] sbl0off_l middle 14 bits of 18-bi t sequential block 0 offset (sbl0off[15:2]) [1] sbl0off_1 sbl0off[1]. its is fixed to 0 when sbf0 is working in 32-bit access mode. [0] sbl0off_0 sbl0off[0]. its is fixed to 0. * note: when sbl0off is written sbl0off[1:0] is set as ?00? because the boundary of sbl0 was fixed to be word (32-bit data) aligned for efficient system memory access. sbl1off_h: higher bits of offset register of sequential block 1 area reset value : 0000h base + 56h mode : read/write bit name description [15:2] - not used (reading returns zero) [1:0] sbl1off_h higher 2 bits of 18-bit sequential block 1 offset (sbl1off[17:16]) sbl1off_l: lower bits of offset register of sequential block 1 area reset value : 0000h base + 58h mode : read/write bit name description [15:2] sbl1off_l middle 14 bits of 18-bi t sequential block 1 offset (sbl1off[15:2]) [1] sbl1off_1 sbl1off[1]. its is fixed to 0 when sbf1 is working in 32-bit access mode. [0] sbl1off_0 sbl1off[0]. its is fixed to 0. * note: when sbl1off is written sbl1off[1:0] is set as ?00? because the boundary of sbl1 was fixed to be word (32-bit data) aligned for efficient system memory access. sbl0begin_h: higher bits of begin offset of sequent ial block 0 area in ring mode reset value : 0000h base + 5ah mode : read/write
calmadm functional spec 40-25 bit name description [15:2] - not used (reading returns zero) [1:0] sbl0begin_h higher 2 bits of 18-bit sequ ential block 0 begin offset (sbl0begin[17:16]) sbl0begin_l: lower bits of begin offset of sequential block 0 area in ring mode reset value : 0000h base + 5ch mode : read/write bit name description [15:2] sbl0begin_l middle 14 bits of 18-bit se quential block 0 begin offset (sbl0begin[15:2]) [1:0] sbl0begin_10 lower 2 bits of 18-bit sequential block 0 begin offset (sbl0begin[1:0]). these are fixed to 00. sbl1begin_h: higher bits of begin offset of sequent ial block 1 area in ring mode reset value : 0000h base + 5eh mode : read/write bit name description [15:2] - not used (reading returns zero) [1:0] sbl1begin_h higher 2 bits of 18-bit sequ ential block 1 begin offset (sbl1begin[17:16]) sbl1begin_l: lower bits of begin offset of sequential block 1 area in ring mode reset value : 0000h base + 60h mode : read/write bit name description [15:2] sbl1begin_l middle 14 bits of 18-bit se quential block 1 begin offset (sbl1begin[15:2]) [1:0] sbl1begin_10 lower 2 bits of 18-bit sequential block 1 begin offset (sbl1begin[1:0]). these are fixed to 00. sbl0end_h: higher bits of end offset of sequential block 0 area in ring mode reset value : 0000h base + 62h mode : read/write bit name description [15:2] - not used (reading returns zero) [1:0] sbl0end_h higher 2 bits of 18-bit sequ ential block 0 end offset (sbl0end[17:16]) sbl0end_l: lower bits of end offset of sequential block 0 area in ring mode reset value : 0000h
functional spec calmadm 40-26 base + 64h mode : read/write bit name description [15:2] sbl0end_l middle 14 bits of 18-bit sequential block 0 end offset (sbl0end[15:2]) [1:0] sbl0end_10 lower 2 bits of 18-bit sequential blo ck 0 end offset (sbl0end[1:0]). these are fixed to 00. sbl1end_h: higher bits of end offset of sequential block 1 area in ring mode reset value : 0000h base + 66h mode : read/write bit name description [15:2] - not used (reading returns zero) [1:0] sbl1end_h higher 2 bits of 18-bit sequ ential block 1 end offset (sbl1end[17:16]) sbl1end_l: lower bits of end offset of sequential block 1 area in ring mode reset value : 0000h base + 68h mode : read/write bit name description [15:2] sbl1end_l middle 14 bits of 18-bit sequential block 1 end offset (sbl0end[15:2]) [1:0] sbl1end_10 lower 2 bits of 18-bit sequential blo ck 1 end offset (sbl0end[1:0]). these are fixed to 00. register set 5: sfrsi function registers sfrbstat0/1/2: sfr buffer state register reset value : 0xxxh base + 6ah, 70h, 76h mode : read/write bit name description [15:13] - not used (reading returns zero) [12] sfrbvalid this flag is set as high only when sfr buffer contains valid read/write data. [11:9] - not used (reading returns zero) [8] sfrbmode 0: read mode 1: write mode this flag is effective only when sfrbvalid flag is set as high. [7:6] - not used (reading returns zero)
calmadm functional spec 40-27 [5:0] sfrbtag[21:16] higher 6 bits of sfr buffer tag address sfrbtag0/1/2: sfr tag address regist er reset value : xxxxh base + 6ch, 72h, 78h mode : read/write bit name description [15:0] sfrbtag[15:0] lower 16 bi ts of sfr buffer tag address sfrbuf0/1/2: sfr data register reset value : xxxxh base + 6eh, 74h, 7ah mode : read/write bit name description [15:0] sfrbuf sfr data buffer register set 6: dhclk control dhclk_con: dhclk delay control register reset value : 0000h base + 7ch mode : read/write bit name description [15:3] - not used (reading returns zero) [2:0] dhclk_con dhclk (clock of i-cache memories) delay control value 3 calmadm3 hardware specifications 3-1 interface spec.
functional spec calmadm 40-28 3-1-1 pin descriptions table 3-1. calmadm3 pin description group signal direction polarity description nres i low reset signal mclk i rising clock nsysid o low sys command indicator da[4:0] o - da output for sys commands pmode o high privileged mode indicator nirq i low interrupt request nfiq i low fast interrupt request system interface nexpack o low acknowledge for exceptions hbusreqm o high hgrantm i high hreadym i high haddrm [31:0] o - htransm [1:0] o - hburstm [3:0] o - hsizem [2:0] o - hwritem o high hwdatam[31:0] o - ahb master interface hrdatam[31:0] i - ntrst i low tck i rising tms i - tdi i - tdo o - nres_dbu o low reset signal from dbu in adm debug interface runst_dbu o high indicating calm is not stopped by dbu bistmode i - memsel[2:0] i - bclk i - bist_on i high bist input signals diag_bist_xyc o - done_bist_xyc o - errob_bist_xyc o - pause_bist_xyc o - bist output signals for x and y-cache memories diag_bist_ic o - done_bist_ic o - errob_bist_ic o - bist interface pause_bist_ic o - bist output signals for i-cache memories scan_test_mode i high scan_enable i high scan test interface scan_in i -
calmadm functional spec 40-29 scan_out o - 3-1-2 pin timing diagrams *will be available in later release if necessary 3-2 arbiter features prioritized scheduling of bus requests from 8 sources sfrsi (the highest priority) > sbf0 > sbf1 > x-cache > y-cache > i-cache > x-cache write-back > y-cache write-back (the lowest priority) 3-3 ahbmiu (ahb master interface unit) features - eight burst word access to system memory for i-cache - six burst word access to system memory for x/y-caches - single burst half-word and byte access to system memory for cache bypass mode. - one ~ four burst word access for sequential accesses to sequential blocks - single burst half-word access for random accesses to sequential blocks - single burst word access to sfrs
functional spec calmadm 40-30 3-4 instruction cache overview i-cache is a direct-mapped, 128x 16-instruction size cache. three commands, on, off and all-invalidation, are suppor ted for normal cache function. before i-cache on, all- invalidation command should be done. i-cache also supports one-line-invalidation function for debugging convenience. if calm performs ldc instruction while ?ldc inv? flag of admcfg register is on, one i-cache line selected by program address of calm is invalidated. since i-cache performs caching with virtual address (cal m program memory address), it is need to convert to physical address (system memory addr ess). this conversion is done inside of i-cache by adding cache address with the base field of corresponding region c onfiguration register (r0cfg ~ r7cfg). features - direct-mapped cache - 128 data entries (cache lines) - 256-bit wide data memory (16 half-word instructions in a cache line) - 11-bit wide tag memory (10-bit tag address + 1 valid bit) - 24-bit base fields for mapping to physical address - supports all invalidation and one line invalidation 3-5 data caches in adm are two data caches. one is x-cache caching data in mac x area. the other is y-cache caching data in mac y area. since, x-cache and y-cache are exactly sa me, only x-cache is described more detail in this section. these two data caches also works as the data ca che for calm area as a kind of 4-way set-associative cache. 3-5-1 x-cache overview x-cache is a 2-way set associative cache with a set sized 128x8-data.
calmadm functional spec 40-31 four commands, on, off, invalidation a nd flush, are supported for normal cach e function. before x-cache on, all- invalidation command should be done. after x-cache off, flush command should be done to keep system memory data consistency. since x-cache performs caching with virtual address (mac x memory address), it is need to be converted to physical address (host memory address). the physical address is an addition of 4:3 reduced virtual address with x-area base (xbase). x-cache works as not only the cache for mac x area data accessed by both calm and mac but also the cache for calm area data accessed by calm only. features - 2-way set associative cache - 128 data entries (cache lines) in a set - 8 audwords (192 bit) in a cache line - only 128 bits of 192-bit cache line are used as calm area cache - 24-bit wide cache tag memory ((11-bit tag address + 1 valid bit) * 2 sets) - 256 dirty flags (for 128 lines * 2 sets) - 24-bit base fields for mapping to physical address - supports invalidation and flushing. 3-5-2 x/y-cache as calm area data cache overview x/y-caches work as not only the cache for mac x/y area data accessed by both calm and mac but also the cache for calm area data accessed by calm only. by setting xyrr code in admcfg register properly, x- and y- cache can be enabled/disabled as the cache of calm. since x/y-caches perform caching with virtual address (calm data memory address), virtual address to physical address (host memory address) conversion is needed. this conversion is done inside of x/y-cache by adding cache address with the base field of corresponding region c onfiguration register (r8cfg ~ r11cfg). operations when x/y-caches work as the cache for calm area data, the operation is depends on the value of xyrr bits in admcfg register. - when x-cache is selected (xyrr == 01) calm area data are accessed through x-cache block whether its cache function is enabled or not.
functional spec calmadm 40-32 - when y-cache is selected (xyrr == 1x) calm area data are accessed through y-cache block whether its cache function is enabled or not. - when round robin scheme is selected (xyrr == 00) if both of x- and y- caches are enabled, x- and y-cache are selected for cache data replacement one after another (round robin). at the first miss, x-cache is selected for replacement. when next miss occurred, y-cache is selected for replacement. at the next miss, x-cache is selected, and so on. if both of x- and y- caches are disabled, calm area data are accessed through y-cache block. if one of x- and y- caches is enabled and the other one is disabled, calm area data are accessed through enabled cache block. architecture when x/y-caches work as the cache for calm area data, t he architecture of the cache is depends on the value of xyrr bits in admcfg register. following description is for the case when both x- and y- caches are enabled. - when one of x- or y-cache is selected (xyrr == 01 or xyrr == 1x) z 4k byte, 2-way set associative cache z 128 data entries (cache lines) in a set z 8 half-words (128 bit) in a cache line - when round robin scheme is selected (xyrr == 00) z 8k byte, 4-way set associative cache z 128 data entries (cache lines) in a set z 8 half-words (128 bit) in a cache line 3-6 sbfu (s-buffer unit) overview in adm, two sequential buffers, sbf0 and sbf1, are includ ed. a sequential buffer consists of a 128-bit fifo, a 18-bit offset register, two 18-bit boundary offset registers and a 16-bit data buffer. 128-bit fifo is used as buffer when mac sequentially access es sequential block. a 16-bit data register is used as buffer when calm randomly accesses sequential block. 18-b it offset register contains offset address of sequential block data to be accessed. since it is defined in hfrs, us er can write the start address of sequential block into
calmadm functional spec 40-33 this register. this register is added with base field of the region configuration re gister (s0cfg, s1cfg) to generate physical address of sequential data. after a sequent ial access to sequential block has done, this register value is increased automatically. this increment is modulated by the size limit defined in size field of the region configuration register (s0cfg, s1cfg). in ring mode, aut o-incremented register value is compared with 18-bit end offset register value. if these are same, offset register is set as 18-bit begin offset register value and interrupt flag in admstat register is set. two special commands, fill and flush, are supported for a sequential buffer. before user starts sequential read on sequential block, fill command should be done. flus h command should be done after sequential writes end. access mode, unit data size and data size conversion sc heme in a sbfu are defined in admcfg register. more of sbfu operation is described in 2-2. features - 4-word fifo used as a sequential buffer - 18-bit offset address register : automatically increased during sequential accesses : the increment is modulated according to the size field - 16-bit data buffer for random access to sequential block area - fill and flush commands - unit data size and data size conversion sc heme selected by setting control flags. - two access modes supported (linear mode and ring mode) - two boundary offset registers (begin offset and end offset) are used in the ring mode. 3-7 sfrsi (sfrs interface unit) features - one-entry cache composed of : sfrbuf[15:0]: sfr read/write buffer : sfrbtag[21:0]: sfrbuf tag address : sfrbvalid: ?0? ? invalid, ?1? ? valid : sfrbmode: ?0? ? read mode, ?1? ? write mode - one-entry cache with : auto-invalidation on hit : auto-backup on exception : recovery on ?sys_rsfrb? command - backup stack : depth = 2 (for two exceptions, irq and fiq)
functional spec calmadm 40-34 : contains all components of the one-entry cache - all registers and flags in the one-entry cache and the stack are defined in hfrs : for debugging and context switching purpose 4 constraints on using calmadm3 *note: this chapter is exactly same as the one in calm adm2 specification. if you are familiar with calmadm2, you don?t need to read this chapter. 4-1 constraints on using calmrisc16f delay slot instruction as an instruction at delay slot, following 3 types of instructions are prohibited. - break instruction - branch instructions - two word instructions 4-2 constraints on using calmmac24f loading ram pointer because of the nature of pipeline scheme and data memory accessing scheme of mac, data memory accessing with the ram pointer, that is l oaded from the outside of mac just before, is prohibited. an enop instruction or another inst ruction should be inserted between ram pointer load instruction and data memory access instruction using that ram pointer as data address. instructions loading ram pointer are listed in table6-1. example code eld rp0, rpd1.0 ; load ram pointer enop ; inserted enop eld a, @rp0 ; using loaded ram pointer as data address
calmadm functional spec 40-35 table 6-1. list of instructions loading ram pointers opc op1 op2 function flag eld rpui rpd1.adr:2 op1<-op2 - note. opc ? opcode, opi- operand i accessing min/max data for easy searching min/max data, mac offers special instructions, emin and emax. the example code below shows how to search min/m ax data with emin/emax instructions. after the execution of a emin/emax instructi on, the address of min/max data is latched in rp3. because of the nature of pipeline scheme and data memory accessi ng scheme of mac, data memory accessing with rp3, that is latched by execution of emin/emax instruction just before, is prohibited. an enop instruction or another instruction should be insert ed between emin/emax instruction and data memory access instruction using rp3 as data address. emin/emax instructions are listed in table6-2. example code eld c, @rp0+s0 ; 1 st data load loop-start: emax a, c, c, @rp0+s0 ; 1 st max evaluation, 2 nd data load jp loop_start emax a, c ; last max evaluation enop ; inserted enop eld a, @rp3 ; using rp3 as data address table 6-2. list of emin/emax instructions opc op1 op2 op3 op4 function flag emax ai<-max(ai,ci), op3<-o p4, rp3<-addr ess v,n,z,c emin ai ci ci @rps ai<-min(ai,ci), op3<-op4, rp3<- address v,n,z,c note. opc ? opcode, opi- operand i 4-3 constraints on access ing sequential buffers data alignment
functional spec calmadm 40-36 when calm accesses sequential block area, the data can be byte or half word. when mac access sequential buffer, the data can be half word aligned or word aligned. however, when fill or flush is performed in sequentia l buffer, adm assumes the data is word aligned. this assumption was taken for efficient external memory access. when user accesses a sequential buffer in half word mode, odd number of sequential accesses causes miss-aligned external memory access. there is no hardware to prevent odd number of sequential accesses in adm. therefore, user program should consider data alignment, especially for sequential writes in half word mode. sbl0off and sbl1off can be half word aligned or word aligned when these are automatically increased. however, these are fixed to be word aligned when these are written. sbl0begin, sbl0end, sbl1begin are sbl1end are fixed to be word aligned. confirm flush after a flush command is performed, it is recommend ed to check the status flag in sbfstat register if the flush has done physically. this status check is not needed in most cases. however, when adm transmits certain data to host processor through se quential buffer, data coherence may be corrupted if this confirmation is omitted. 4-4 constraints on accessing x/y-caches setting xyrr the xyrr flags in admcfg register should be set while both x-cache and y-ca che are turned off. if the xyrr flags are changed while one or both of x- cache and y-cache are turned on, following data reads and writes may be performed incorrectly. be cause of that, the data in system memory may corrupt. 4-5 definitions of abbreviations instruction tables in this chapter ar e extracted from ?3.3 quick reference? instruction table in ?calmmac24 dsp coprocessor architecture reference manual?. definition of abbreviations used in instruction tables is listed following tables. this tables are copy of ?3.2 instruct ion coding, (1) abbreviation definition and encoding? of ?calmmac24 dsp coprocessor architecture reference manual?. ? rps mnemonic encoding description
calmadm functional spec 40-37 rp0+s0 000 rp0 post-modified by sd0 s0 field rp1+s0 001 rp1 post-modified by sd1 s0 field rp2+s0 010 rp2 post-modified by sd2 s0 field rp3+s0 011 rp3 post-modified by sd3 s0 field rp0+s1 100 rp0 post-modified by sd0 s1 field rp1+s1 101 rp1 post-modified by sd1 s1 field rp2+s1 110 rp2 post-modified by sd2 s1 field rp3+s1 111 rp3 post-modified by sd3 s1 field ? rpd mnemonic encoding description rp0+d0 000 rp0 post-modified by sd0 d0 field rp1+d0 001 rp1 post-modified by sd1 d0 field rp2+d0 010 rp2 post-modified by sd2 d0 field rp3+d0 011 rp3 post-modified by sd3 d0 field rp0+d1 100 rp0 post-modified by sd0 d1 field rp1+d1 101 rp1 post-modified by sd1 d1 field rp2+d1 110 rp2 post-modified by sd2 d1 field rp3+d1 111 rp3 post-modified by sd3 d1 field ? rp01s mnemonic encoding description rp0+s0 00 rp0 post-modified by sd0 s0 field rp1+s0 01 rp1 post-modified by sd1 s0 field rp0+s1 10 rp0 post-modified by sd0 s1 field
functional spec calmadm 40-38 rp1+s1 11 rp1 post-modified by sd1 s1 field ? rp3s mnemonic encoding description rp3+s0 0 rp3 post-modified by sd3 s0 field rp3+s1 1 rp3 post-modified by sd3 s1 field ? mg1 mnemonic encoding description y0 000 y0[23:0] register y1 001 y1[23:0] register x0 010 x0[23:0] register x1 011 x1[23:0] register ma0(h) 100 ma0[51:0] / ma0[47:24] register ma0l 101 ma0[23:0] register ma1(h) 110 ma1[51:0] / ma1[47:24] register ma1l 111 ma1[23:0] register ? mg2 mnemonic encoding description rp0 000 current bank rp0[15:0] register rp1 001 current bank rp1[15:0] register rp2 010 current bank rp2[15:0] register rp3 011 current bank rp3[15:0] register rpd0 100 rpd0[15:0] register rpd1 101 rpd1[15:0] register
calmadm functional spec 40-39 mc0 110 mc0[15:0] register mc1 111 mc1[15:0] register ? sdi mnemonic encoding description sd0 00 current bank sd0[15:0] register (sd0 or sd0e) sd1 01 current bank sd1[15:0] register sd2 10 current bank sd2[15:0] register sd3 11 current bank sd3[15:0] register (sd3 or sd3e) ? ai mnemonic encoding description a 0 a[23:0] register b 1 b[23:0] register ? ci mnemonic encoding description c 0 c[23:0] register d 1 d[23:0] register ? an mnemonic encoding description a 00 a[23:0] register b 01 b[23:0] register c 10 c[23:0] register d 11 d[23:0] register
functional spec calmadm 40-40 ? rpui mnemonic encoding description rp0 0000 current bank rp0[15:0] register rp1 0001 current bank rp1[15:0] register rp2 0010 current bank rp2[15:0] register rp3 0011 current bank rp3[15:0] register mc0_0 0100 mc0[15:0] register (set 0) mc1_0 0101 mc1[15:0] register (set 0) mc0_1 0110 mc0[15:0] register (set 1) mc1_1 0111 mc1[15:0] register (set 1) sd0_0 1000 current bank sd0[15: 0] register (set 0) sd1_0 1001 current bank sd1[15: 0] register (set 0) sd2_0 1010 current bank sd2[15: 0] register (set 0) sd3_0 1011 current bank sd3[15: 0] register (set 0) sd0_1 1100 current bank sd0[15: 0] register (set 1) sd1_1 1101 current bank sd1[15: 0] register (set 1) sd2_1 1110 current bank sd2[15: 0] register (set 1) sd2_1 1111 current bank sd3[15: 0] register (set 1) ? mga mnemonic encoding description ma0 00 ma0[51:0] / ma0[47:24] register ma1 01 ma1[51:0] / ma1[47:24] register a 10 a[23:0] register
calmadm functional spec 40-41 b 11 b[23:0] register ? mgx mnemonic encoding description y0 00 y0[23:0] register y1 01 y1[23:0] register x0 10 x0[23:0] register x1 11 x1[23:0] register 5 information for calmshine development 5-1 simulator spec . memory map simulator should keep track of memory configuration in section 2-1 from calm and mac point of view. - program regions, calm regions, x/y/s0/s1 r egions can be modeled same as the calmadm2 case. - modeling the region control and the address tran slation to system memory space is not needed. - hfrs registers can be modeled t hose read/write function only. modelin g precise functionality of them described in this document is not needed. - exception: some sequential buffer related registers (flags) should be modeled precisely as described in next paragraph. - sfrs area can be modeled as a normal memory area.
functional spec calmadm 40-42 modeling sequential buffers *note: this section is exactly same as the one in calmad m2 specification. if you are familiar with calmadm2, you don?t need to read this section. simulator should keep track of the sequential accesses in 2-2 in terms of the functionality only. modeling exact hardware structure is not needed. - sequential buffer models are not needed in simulator. - sequential offset registers should be modeled in simulator. being read/written as a control register, addres sing sequential block area and auto-increment capability of these registers should be modeled. when written, these registers should be word-aligned. in other words, lower 2 bits of these registers should be forced as 0 when calm writes values to these registers. when auto-incremented, the incrementing step s hould follow the mode defined by flags of admcfg register in hfrs. in ring mode, equivalence between offset register and end offset register should be checked in simulator. in addition, wrapping and flag setting should be done in simulator when those are same. - data format mapping defined by sbf0/1 mode flags should be modeled in simulator. sbf0/1 mode flags are part of admcfg register in hfrs. - modeling commands on sequential buffers, defined by sbfcon register in hfrs, is not needed in simulator. - access mode defined by [3] bits of sbf0/1 mode flags should be modeled in simulator. - begin offset registers and end offset register s should be modeled in simulator as one of memory mapped i/o registers. these should be used for wrap ping operation of offset register in ring mode. - when sbf0mode/sbf1mode flags are written, newly updated values are not effective to the operation of sequential buffers. new values are effective afte r the sequential buffer is newly initialized, which means that sbl0off/sbl1off regi sters are newly written. 5-2 emulator spec. accessing sfrs because of hardware limitation of sfrsi block, sfrs area should be accessed in 16-bit mode only. byte-read from sfrs area always returns zero. byte-write to sfrs area is same as no-operation.
S5L840F (preliminary spec) gpio ports 10-1 10 gpio ports overview S5L840F has 72 multi-functional gpio (general-purpose i nput/output) port pins organized into ten port groups: each port can be easily configured by software to meet various system configurat ion and design requirements. these multi-functional pins need to be properly configured bef ore their use. if a multiplexed pin is not used as a dedicated functional pin, this pin can be configured as gpio ports. the initial pin states, before pin configurations, are configured elegantly to avoid some problems.
gpio ports S5L840F (preliminary spec) 10-2 table 10-1. port configuration overview port 0 selectable pin functions function 1 function 2 function 3 pin no. gpio pin_name i/o module pin _name i/o module p0.0 38 input/output tack/tacap i timer ? p0.1 39 input/output taout o timer ? p0.2 40 input/output tcck i timer ? p0.3 41 input/output spdif o spdif ? p0.4 31 input/output rx i uart ? p0.5 32 input/output tx o uart ? p0.6 42 input/output eint6 i icu sdwp i sdc p0.7 43 input/output eint7 i icu nf_rbn i nf port 1 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p1.0 108 input/output mosi i/o spi ? p1.1 109 input/output miso i/o spi ? p1.2 110 input/output spiclk i/o spi ? p1.3 115 input/output scl i/o iic ? p1.4 116 input/output sda i/o iic ? p1.5 117 input/output nssi i spi ? p1.6 10 input/output eint4 i icu ? p1.7 11 input/output eint5 i icu ? port 2 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p2.0 48 input/output eint0 i icu ? p2.1 49 input/output eint1 i icu ? p2.2 50 input/output eint2 i icu ? p2.3 51 input/output eint3 i icu ?
S5L840F (preliminary spec) gpio ports 10-3 table 10-1. port configuration overview (continued) port 3 selectable pin functions function 1 function 2 function 3 pin no. gpio pin_name i/o module pin _name i/o module p3.0 61 input/output ck_sdc_mm c o sdc/mmc ? p3.1 73 input/output ck_ms o ms ? port 4 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p4.0 56 input/output io0 i/o smc ? p4.1 58 input/output io1 i/o smc ? p4.2 60 input/output io2 i/o smc ? p4.3 63 input/output io3 i/o smc ? p4.4 69 input/output io4 i/o smc ? p4.5 71 input/output io5 i/o smc ? p4.6 74 input/output io6 i/o smc ? p4.7 76 input/output io7 i/o smc ? port 5 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p5.0 57 input/output io8 i/o smc d1 ? sdc/mmc p5.1 59 input/output io9 i/o smc d0 ? sdc p5.2 62 input/output io10 i/o smc cmd ? sdc/mmc p5.3 64 input/output io11 i/o smc d3 ? sdc p5.4 70 input/output io12 i/o smc d2 ? sdc p5.5 72 input/output io13 i/o smc ? p5.6 75 input/output io14 i/o smc d0 ? ms p5.7 77 input/output io15 i/o smc bs ? ms
gpio ports S5L840F (preliminary spec) 10-4 table 10-1. port configuration overview (continued) port 6 selectable pin functions function 1 function 2 function 3 pin no. gpio pin_name i/o module pin _name i/o module p6.0 78 input/output nre o smc ? p6.1 79 input/output nce0 o smc ? p6.2 80 input/output nce1 o smc ? p6.3 81 input/output nce2 o smc ? p6.4 82 input/output cle o smc ? p6.5 83 input/output ale o smc ? p6.6 84 input/output nwe o smc ? p6.7 85 input/output nwp o smc ? port 7 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p7.0 86 input/output sdi i iis ? p7.1 87 input/output ws o iis ? p7.2 90 input/output sdo o iis ? p7.3 91 input/output sclk o iis ? p7.4 92 input/output mclk o iis ? port 8 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p8.0 18 input/output ld0 o lcd ? p8.1 24 input/output ld1 o lcd ? p8.2 25 input/output ld2 o lcd ? p8.3 26 input/output ld3 o lcd ? p8.4 27 input/output ld4 o lcd ? p8.5 28 input/output ld5 o lcd ? p8.6 29 input/output ld6 o lcd ? p8.7 30 input/output ld7 o lcd ?
S5L840F (preliminary spec) gpio ports 10-5 table 10-1. port configuration overview (continued) port 9 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p9.0 33 input/output re o lcd ? p9.1 34 input/output we o lcd ? p9.2 35 input/output cs o lcd ? p9.3 36 input/output reg o lcd ? p9.4 37 input/output reset o lcd ? port 10 selectable pin functions function 1 function 2 function 3 pin no. gpio pin _name i/o module pin _name i/o module p10.0 93 input/output ? ? p10.1 94 input/output ? ? p10.2 95 input/output ? ? p10.3 96 input/output ? ? p10.4 104 input/output ? ? p10.5 105 input/output ? ? p10.6 106 input/output ? ? p10.7 107 input/output ? ?
gpio ports S5L840F (preliminary spec) 10-6 port control descriptions port configuration register (pcon0 ? pcon10) in S5L840F, most pins are multiplexed, and the pconn ( port control register) determi nes which function is used for each pin. if p0.6-p0.7 is used for the wakeup signal in power dow n mode, these ports must be configured for interrupt mode. port data register (pdat0 ? pdat10) if ports are configured as output ports, data can be wri tten to the corresponding bit of pdatn. if ports are configured as input ports, the data can be read from the corresponding bit of pdatn. external interrupt control register the 8 external interrupts support various trigger mode: the trigger mode can be configured as falling-edge trigger and rising-edge trigger. because each external interrupt pin has an integrated digita l noise filter, the interrupt controller can recognize the request signal that lasts longer than 3 clocks.
S5L840F (preliminary spec) gpio ports 10-7 gpio port special function registers port 0 control registers (pcon0, pdat0) register address r/w description reset value pcon0 0x3cf0 0000 r/w configures the pins of port 0 0x0000 0000 pdat0 0x3cf0 0004 r/w the data register for port 0 undefined pcon0 bit description p0.0 [1:0] 00 = input 01 = output 10 = tack/tacap(timer) 11 = not used p0.1 [3:2] 00 = input 01 = output 10 = taout(timer) 11 = not used p0.2 [5:4] 00 = input 01 = output 10 = tcck(timer) 11 = not used p0.3 [7:6] 00 = input 01 = output 10 = spdif(spdif) 11 = not used p0.4 [9:8] 00 = input 01 = output 10 = rx(uart) 11 = not used p0.5 [11:10] 00 = input 01 = output 10 = tx(uart) 11 = not used p0.6 [13:12] 00 = input 01 = output 10 = eint6(icu) 11 = sdwp(sdc) p0.7 [15:14] 00 = input 01 = output 10 = eint7(icu) 11 = nf_rbn(smc) pdat0 bit description p0[7:0] [7:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
gpio ports S5L840F (preliminary spec) 10-8 port 1 control registers (pcon1, pdat1) register address r/w description reset value pcon1 0x3cf0 0010 r/w configures the pins of port 1 0x0000 0000 pdat1 0x3cf0 0014 r/w the data register for port 1 undefined pcon1 bit description p1.0 [1:0] 00 = input 01 = output 10 = mosi(spi) 11 = not used p1.1 [3:2] 00 = input 01 = output 10 = miso(spi) 11 = not used p1.2 [5:4] 00 = input 01 = output 10 = spiclk(spi) 11 = not used p1.3 [7:6] 00 = input 01 = output 10 = scl(iic:open drain) 11 = not used p1.4 [9:8] 00 = input 01 = output 10 = sda(iic:open drain) 11 = not used p1.5 [11:10] 00 = input 01 = output 10 = nssi(spi) 11 = not used p1.6 [13:12] 00 = input 01 = output 10 = eint4(icu) 11 = not used p1.7 [15:14] 00 = input 01 = output 10 = eint5(icu) 11 = not used pdat1 bit description p1[7:0] [7:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
S5L840F (preliminary spec) gpio ports 10-9 port 2 control registers (pcon2, pdat2) register address r/w description reset value pcon2 0x3cf0 0020 r/w configures the pins of port 2 0x0000 0000 pdat2 0x3cf0 0024 r/w the data register for port 2 undefined pcon2 bit description p2.0 [1:0] 00 = input 01 = output 10 = eint0(icu) 11 = not used p2.1 [3:2] 00 = input 01 = output 10 = eint1(icu) 11 = not used p2.2 [5:4] 00 = input 01 = output 10 = eint2(icu) 11 = not used p2.3 [7:6] 00 = input 01 = output 10 = eint3(icu) 11 = not used pdat2 bit description p2[3:0] [3:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
gpio ports S5L840F (preliminary spec) 10-10 port 3 control registers (pcon3, pdat3) register address r/w description reset value pcon3 0x3cf0 0030 r/w configures the pins of port 3 0x0000 0000 pdat3 0x3cf0 0034 r/w the data register for port 3 undefined pcon3 bit description p3.0 [1:0] 00 = input 01 = output 10 = ck_sdc(sdc/mmc) 11 = not used p3.1 [3:2] 00 = input 01 = output 10 = ck_ms(ms) 11 = nout used pdat3 bit description p3[1:0] [1:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
S5L840F (preliminary spec) gpio ports 10-11 port 4 control registers (pcon4, pdat4) register address r/w description reset value pcon4 0x3cf0 0040 r/w configures the pins of port 4 0x0000 0000 pdat4 0x3cf0 0044 r/w the data register for port 4 undefined pcon4 bit description p4.0 [1:0] 00 = input 01 = output 10 = io0(smc) 11 = not used p4.1 [3:2] 00 = input 01 = output 10 = io1(smc) 11 = not used p4.2 [5:4] 00 = input 01 = output 10 = io2(smc) 11 = not used p4.3 [7:6] 00 = input 01 = output 10 = io3(smc) 11 = not used p4.4 [9:8] 00 = input 01 = output 10 = io4(smc) 11 = not used p4.5 [11:10] 00 = input 01 = output 10 = io5(smc) 11 = not used p4.6 [13:12] 00 = input 01 = output 10 = io6(smc) 11 = not used p4.7 [15:14] 00 = input 01 = output 10 = io7(smc) 11 = not used pdat4 bit description p4[7:0] [7:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
gpio ports S5L840F (preliminary spec) 10-12 port 5 control registers (pcon5, pdat5) register address r/w description reset value pcon5 0x3cf0 0050 r/w configures the pins of port 5 0x0000 0000 pdat5 0x3cf0 0054 r/w the data register for port 5 undefined pcon5 bit description p5.0 [1:0] 00 = input 01 = output 10 = io8(smc) 11 = d1(sdc/mmc) p5.1 [3:2] 00 = input 01 = output 10 = io9(smc) 11 = d0(sdc) p5.2 [5:4] 00 = input 01 = output 10 = io10(smc) 11 = cmd(sdc/mmc) p5.3 [7:6] 00 = input 01 = output 10 = io11(smc) 11 = d3(sdc) p5.4 [9:8] 00 = input 01 = output 10 = io12(smc) 11 = d2(sdc) p5.5 [11:10] 00 = input 01 = output 10 = io13(smc) 11 = not used p5.6 [13:12] 00 = input 01 = output 10 = io14(smc) 11 = d0(ms) p5.7 [15:14] 00 = input 01 = output 10 = io15(smc) 11 = bs(ms) pdat5 bit description p5[7:0] [7:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
S5L840F (preliminary spec) gpio ports 10-13 port 6 control registers (pcon6, pdat6) register address r/w description reset value pcon6 0x3cf0 0060 r/w configures the pins of port 6 0x0000 0000 pdat6 0x3cf0 0064 r/w the data register for port 6 undefined pcon6 bit description p6.0 [1:0] 00 = input 01 = output 10 = nre(smc) 11 = not used p6.1 [3:2] 00 = input 01 = output 10 = nce0(smc) 11 = not used p6.2 [5:4] 00 = input 01 = output 10 = nce1(smc) 11 = not used p6.3 [7:6] 00 = input 01 = output 10 = nce2(smc) 11 = not used p6.4 [9:8] 00 = input 01 = output 10 = cle(smc) 11 = not used p6.5 [11:10] 00 = input 01 = output 10 = ale(smc) 11 = not used p6.6 [13:12] 00 = input 01 = output 10 = nwe(smc) 11 = not used p6.7 [15:14] 00 = input 01 = output 10 = nwp(smc) 11 = not used pdat6 bit description p6[7:0] [7:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
gpio ports S5L840F (preliminary spec) 10-14 port 7 control registers (pcon7, pdat7) register address r/w description reset value pcon7 0x3cf0 0070 r/w configures the pins of port 7 0x0000 0000 pdat7 0x3cf0 0074 r/w the data register for port 7 undefined pcon7 bit description p7.0 [1:0] 00 = input 01 = output 10 = sdi(iis) 11 = not used p7.1 [3:2] 00 = input 01 = output 10 = ws(iis) 11 = not used p7.2 [5:4] 00 = input 01 = output 10 = sdo(iis) 11 = not used p7.3 [7:6] 00 = input 01 = output 10 = sclk(iis) 11 = not used p7.4 [9:8] 00 = input(eint4) 01 = output 10 = mclk(iis) 11 = not used pdat7 bit description p7[4:0] [4:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
S5L840F (preliminary spec) gpio ports 10-15 port 8 control registers (pcon8, pdat8) register address r/w description reset value pcon8 0x3cf0 0080 r/w configures the pins of port 8 0x0000 0000 pdat8 0x3cf0 0084 r/w the data register for port 8 undefined pcon8 bit description p8.0 [1:0] 00 = input 01 = not used 10 = ld0(lcd) 11 = not used p8.1 [3:2] 00 = input 01 = not used 10 = ld1(lcd) 11 = not used p8.2 [5:4] 00 = input 01 = not used 10 = ld2(lcd) 11 = not used p8.3 [7:6] 00 = input 01 = not used 10 = ld3(lcd) 11 = not used p8.4 [9:8] 00 = input 01 = not used 10 = ld4(lcd) 11 = not used p8.5 [11:10] 00 = input 01 = not used 10 = ld5(lcd) 11 = not used p8.6 [13:12] 00 = input 01 = not used 10 = ld6(lcd) 11 = not used p8.7 [15:14] 00 = input 01 = not used 10 = ld7(lcd) 11 = not used pdat8 bit description p8[7:0] [3:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
gpio ports S5L840F (preliminary spec) 10-16 port 9 control registers (pcon9, pdat9) register address r/w description reset value pcon9 0x3cf0 0090 r/w configures the pins of port 9 0x0000 0000 pdat9 0x3cf0 0094 r/w the data register for port 9 undefined pcon5 bit description p9.0 [1:0] 00 = input 01 = output 10 = re(lcd) 11 = not used p9.1 [3:2] 00 = input 01 = output 10 = we(lcd) 11 = not used p9.2 [5:4] 00 = input 01 = output 10 = cs(lcd) 11 = not used p9.3 [7:6] 00 = input 01 = output 10 = reg(lcd) 11 = not used p9.4 [9:8] 00 = input 01 = output 10 = reset(lcd) 11 = not used pdat5 bit description p9[4:0] [4:0] when the port is configured as output port, the pi n state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
S5L840F (preliminary spec) gpio ports 10-17 port 10 control registers (pcon10, pdat10) register address r/w description reset value pcon10 0x3cf0 00a0 r/w configur es the pins of port 5 0x0000 0000 pdat10 0x3cf0 00a4 r/w the data register for port 5 undefined pcon5 bit description p10.0 [1:0] 00 = input 01 = output 1x = not used p10.1 [3:2] 00 = input 01 = output 1x = not used p10.2 [5:4] 00 = input 01 = output 1x = not used p10.3 [7:6] 00 = input 01 = output 1x = not used p10.4 [9:8] 00 = input 01 = output 1x = not used p10.5 [11:10] 00 = input 01 = output 1x = not used p10.6 [13:12] 00 = input 01 = output 1x = not used p10.7 [15:14] 00 = input 01 = output 1x = not used pdat5 bit description p10[7:0] [7:0] when the port is configured as output port, the pin state is the same as the corresponding bit. when the port is configured as functional pin, the undefined value will be read.
gpio ports S5L840F (preliminary spec) 10-18 eintpol (external interrupt polarity control register) the extintr register selects the trigger types among vari ous level or edge trigger mode of the external interrupt. register address r/w description reset value extpol 0x39c0 0018 r/w external interrupt control register 0x0000 0000 extintr bit description p2.0/int0 [0] trigger mode of the extint0. 0 = falling edge triggered 1 = rising edge triggered p2.1/int1 [1] trigger mode of the extint1. 0 = falling edge triggered 1 = rising edge triggered p2.2/int2 [2] trigger mode of the extint2. 0 = falling edge triggered 1 = rising edge triggered p2.3/int3 [3] trigger mode of the extint3. 0 = falling edge triggered 1 = rising edge triggered p1.6/int4 [4] trigger mode of the extint4. 0 = falling edge triggered 1 = rising edge triggered p1.7/int5 [5] trigger mode of the extint5. 0 = falling edge triggered 1 = rising edge triggered p0.6/int6 [6] trigger mode of the extint6. 0 = falling edge triggered 1 = rising edge triggered p0.7/int7 [7] trigger mode of the extint7. 0 = falling edge triggered 1 = rising edge triggered notes : 1. because each external interrupt pins has a digital filter, the interrupt contro ller can recognize a request signal that is longer than 3 clocks. 2. if users want to change the trigger m ode in the external interrupt mode, user s are first required to switch the corresponding pin to input mode and then change the trigger mode.
S5L840F (preliminary spec) gpio ports 10-19 notes
icu preliminary specification S5L840Fx flash type mp3 decoder 30-1 icu (interrupt control unit) user?s manual rev0.0 kim, hye-ryeong media player pj system lsi business device solution network division samsung electronics
icu preliminary specification S5L840Fx flash type mp3 decoder 30-2 2.17.1 functional description the interrupt controller in S5L840F receives the request from 32interrupt sources. these interrupt sources are provided by internal peripheral such as the dma controller, uart, iic, external interrupts, etc. the role of the interrupt controller is to ask for the fiq or irq interrupt requests to the arm940t core after the arbitration process when there are mult iple interrupt requests from internal peripherals and external interrupt request pins. the arbitration process is performed by the hardware priority logic and the result is written to the interrupt pending register and users refer this register to know which interrupt has been requested. source pending register 32 interrupt mask register 32 32 masking logic interrupt mode register mode filter 32 32 irq priority register irq pending register arbiter 32 32 32 nfiq nirq 1 1 interrupt sources[31:0] = {int[27:1], |(eint[7:3]), int[0], eint[2:0]}

interrupt process diagram
icu preliminary specification S5L840Fx flash type mp3 decoder 30-3 interrupt sources icu supports 28 internal interrupt sour ces and 8 external interrupt sources. but 5 external interrupt sources are ored to 1 source internally. therefore, 28 internal interru pt sources, 1 ored external so urce and 3 external sources participate in arbitration. all interrupt sources should be high active and more than 1 cycle pulse signals. therefore, additional logic is needed for external interrupts. additional logic can ma ke external interrupts change signal polarity and be distinguished from invalid sources that were generate d by noise or masked by user control register. interrupt controller operation f-bit and i-bit of psr (program status register) if the f-bit of psr (program status regi ster in arm940t cpu) is set to 1, the cpu does not accept the fiq (fast interrupt request) from the interrupt controller. if i-bit of psr (program status register in arm940t cpu) is set to 1, the cpu does not accept the irq (interrupt request) from the interrupt controller. so, to enable the interrupt reception, the f-bit or i-bit of psr has to be cleared to 0 and also the corresponding bit of intmsk has to be set to 1. interrupt mode arm940t has 2 types of interrupt mode, fiq or irq. all the interrupt sources determine the mode of interrupt to be used at interrupt request. interrupt pending register S5L840F has two interrupt pending resisters. the one is source pending register( srcpnd ) and the other is interrupt pending register( intpnd ). these pending registers indicate whether or not an interrupt request is pending. when the interrupt sources request interrupt servic e the corresponding bits of srcpnd register are set to 1, at the same time the only one bit of intpnd register is set to 1 automatically after arbitration process. if interrupts are masked, the corresponding bits of srcpnd regi ster are set to 1, but the bit of intpnd register is not changed. when a pending bit of intpnd register is set, the interrupt service routine starts whenever the i-flag or f-flag is cleared to 0. the srcpnd and intpnd regist ers can be read and written, so the service routine must clear the pending condition by writing a 1 to the corresponding bit in srcpnd register first and then clear the pending condition in intpnd registers with same method. interrupt mask register indicates that an interrupt has been dis abled if the corresponding mask bit is 0. if an interrupt mask bit of intmsk
icu preliminary specification S5L840Fx flash type mp3 decoder 30-4 is 1, the interrupt will be serviced norm ally. if the corresponding mask bit is 0 and the in terrupt is generated, the source pending bit will be set. interrupt priority generating block the priority logic for 32 interrupt requests is composed of seven rotation-based arbiters: six first-level arbiters and one second-level arbiter as shown in the following figure. arbiter6 arbiter0 arm irq arbiter1 arbiter2 arbiter3 arbiter4 arbiter5 req4/int_timerc req5/ reserved req5/ reserved req0 req1 req2 req3 req4 req5 req1/eint0 req2/eint1 req3/eint2 req4/dbg_wakeup req0/eintg req1/int_timera req2/int_wdt req3/ reserved req0/int_dma req3/ reserved req2/int_pri_rtc req1/int_alarm_rt c req4/int_miu req0/ reserved req1/ reserved req3/ reserved req2/ reserved req4/ reserved req5/ reserved req0/int_uart0 req1/int_spdif req2/ reserved req3/int_lcd req4/int_spi req5/int_iic req1/ reserved req2/int_mstick req3/int_usb req4/int_adc

priority generating block
icu preliminary specification S5L840Fx flash type mp3 decoder 30-5 interrupt priority each arbiter can handle six interrupt requests based on the one bit arbiter mode control(arb_mode) and two bits of selection control signals(arb_sel) as follows: if arb_sel bits are 00b, the priority orde r is req0, req1, req2, req3, req4, and req5. if arb_sel bits are 01b, the priority orde r is req0, req2, req3, req4, req1, and req5. if arb_sel bits are 10b, the priority orde r is req0, req3, req4, req1, req2, and req5. if arb_sel bits are 11b, the priority orde r is req0, req4, req1, req2, req3, and req5. note that req0 of an arbiter is always the highest prio rity, and req5 is the lowest one. in addition, by changing the arb_sel bits, we can rotate the priority of req1 - req4. here, if arb_mode bit is set to 0, arb_sel bits are not automatically chan ged, thus the arbiter operates in the fixed priority mode. (note that even in this mode, we can change the priority by manually changing the arb_sel bits.). on the other hand, if arb_mode bit is 1, arb_sel bits are changed in rotation fashion, e.g., if req1 is serviced, arb_sel bits are changed to 01b automatically so as to make req1 the lowest priority one. the detailed rule of arb_sel change is as follows. if req0 or req5 is serviced, arb_ sel bits are not changed at all. if req1 is serviced, arb_sel bits are changed to 01b. if req2 is serviced, arb_sel bits are changed to 10b. if req3 is serviced, arb_sel bits are changed to 11b. if req4 is serviced, arb_sel bits are changed to 00b. dbg operation mode dbgack occurs during o peration of debugger unit in calmadm3. dbgack signal makes that pending in terrupts is not propagated to calmadm3. if dbgack signal is active( set to 0), both nirq and nfiq is masked to 1. dbgack_hclk is sync hronized with hclk and stop the watchdog-timer operation.
icu preliminary specification S5L840Fx flash type mp3 decoder 30-6 2.17.3 register map there are 9 control regi sters in the interrupt controller: source p ending register, interrupt mode register, mask register, priority register, interrupt pending register, offs et register, external interrupt polarity register, external interrupt mask register and external interrupt pending register. all the interrupt requests from the inte rrupt sources are first registered in the source pending register. they are divided into two groups based on the interrupt mode register, i.e., one fiq request and the remaining irq requests. arbitration process is performed for the mult iple irq requests based on the priority register. source pending register (srcpnd) srcpnd register is composed of 32 bits each of which is re lated to an interrupt source. each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. by reading this register, we can see the in terrupt sources waiting for their requests to be serviced. note that each bit of srcpnd register is automatically set by the interru pt sources regardless of the masking bits in the intmask register. in addition, it is not affected by the priority logic of interrupt controller. in the interrupt service routine for a specific interrupt source, the corresponding bit of srcpnd register has to be cleared to get the interrupt request from the same source correctly. if you return from the isr without clearing the bit, interrupt controller operates as if another interrupt requ est comes in from the same source. in other words, if a specific bit of srcpnd register is set to 1, it is al ways considered as a valid interrupt request waiting to be serviced. the specific time to clear the corresponding bit depends on the user's requirement. the bottom line is that if you want to receive another valid request from the same sour ce you should clear the corresponding bit first, and then enable the interrupt. you can clear a specific bit of srcpnd register by writi ng a data to this register. it clears only the bit positions of srcpnd corresponding to those set to one in the data. the bi t positions corresponding to those that are set to 0 in the data remains as they are with no change register address r/w description reset value srcpnd 0x39c0_0000 r/w indicates t he interrupt request status. 0 = the interrupt has not been requested. 1 = the interrupt source has asserted the interrupt request. 0x00000000
icu preliminary specification S5L840Fx flash type mp3 decoder 30-7 srcpnd bit description initial state int_adc [31] 0 = not requested, 1 = requested 0 int_usb [30] 0 = not requested, 1 = requested 0 int_mstick [29] 0 = not requested, 1 = requested 0 reserved [28] not used 0 int_iic [27] 0 = not requested, 1 = requested 0 int_spi [26] 0 = not requested, 1 = requested 0 int_lcd [25] 0 = not requested, 1 = requested 0 reserved [24] not used 0 int_spdif [23] 0 = not requested, 1 = requested 0 int_uart0 [22] 0 = not requested, 1 = requested 0 reserved [21] not used 0 reserved [20] not used 0 reserved [19] not used 0 reserved [18] not used 0 reserved [17] not used 0 reserved [16] not used 0 reserved [15] not used 0 int_miu [14] 0 = not requested, 1 = requested 0 reserved [13] not used 0 int_pri_rtc [12] 0 = not requested, 1 = requested 0 int_alarm_rtc [11] not used 0 int_dma [10] 0 = not requested, 1 = requested 0 reserved [9] not used 0 int_timer c [8] 0 = not requested, 1 = requested 0 reserved [7] not used 0 int_wdt [6] 0 = not requested, 1 = requested 0 int_timer a [5] 0 = not requested, 1 = requested 0 eintg [4] 0 = not requested, 1 = requested 0 dbg_wakeup [3] 0 = not requested, 1 = requested 0 eint2 [2] 0 = not requested, 1 = requested 0 eint1 [1] 0 = not requested, 1 = requested 0 eint0 [0] 0 = not requested, 1 = requested 0 interrupt mode register (intmod) this register is composed of 32 bits each of which is relat ed to an interrupt source. if a specific bit is set to 1, the corresponding interrupt is processed in the fiq (fast in terrupt) mode. otherwise, it is processed in the irq mode (normal interrupt). note that at most only one interrupt source can be serviced in the fiq mode in the interrupt controller. (you
icu preliminary specification S5L840Fx flash type mp3 decoder 30-8 should use the fiq mode only for the urgent interrupt.) thus, only one bit of intmod can be set to 1 at most. register address r/w description reset value intmod 0x39c0_0004 r/w interrupt mode register. 0 = irq mode 1 = fiq mode 0x00000000 note : if an interrupt mode is set to fiq mode in intmod regi ster, fiq interrupt will not affect intpnd and intoffset registers. the intpnd and intoffset register s are valid only for irq mode interrupt source. intmod bit description initial state int_adc [31] 0 = irq, 1 = fiq 0 int_usb [30] 0 = irq, 1 = fiq 0 int_mstick [29] 0 = irq, 1 = fiq 0 reserved [28] not used 0 int_iic [27] 0 = irq, 1 = fiq 0 int_spi [26] 0 = irq, 1 = fiq 0 int_lcd [25] 0 = irq, 1 = fiq 0 reserved [24] not used 0 int_spdif [23] 0 = irq, 1 = fiq 0 int_uart0 [22] 0 = irq, 1 = fiq 0 reserved [21] not used 0 reserved [20] not used 0 reserved [19] not used 0 reserved [18] not used 0 reserved [17] not used 0 reserved [16] not used 0 reserved [15] not used 0 int_miu [14] 0 = irq, 1 = fiq 0 reserved [13] not used 0 int_pri_rtc [12] 0 = irq, 1 = fiq 0 int_alarm_rtc [11] 0 = irq, 1 = fiq 0 int_dma [10] 0 = irq, 1 = fiq 0 reserved [9] not used 0 int_timer c [8] 0 = irq, 1 = fiq 0 reserved [7] not used 0 int_wdt [6] 0 = irq, 1 = fiq 0 int_timer a [5] 0 = irq, 1 = fiq 0 eintg [4] 0 = irq, 1 = fiq 0 dbg_wakeup [3] 0 = irq, 1 = fiq 0 eint2 [2] 0 = irq, 1 = fiq 0 eint1 [1] 0 = irq, 1 = fiq 0 eint0 [0] 0 = irq, 1 = fiq 0
icu preliminary specification S5L840Fx flash type mp3 decoder 30-9 interrupt mask register (intmsk) each of the 32 bits in the interrupt mask register is relat ed to an interrupt source. if you set a specific bit to 0, the interrupt request from the corresponding interrupt source is not serviced by the cpu. (note that even in such a case, the corresponding bit of srcpnd register is set to 1). if the mask bit is 1, the interrupt request can be serviced. register address r/w description reset value intmsk 0x39c0_0008 r/w determines which interrupt source is masked. the masked interrupt source will not be serviced. 1 = interrupt service is available 0 = interrupt service is masked 0x00000000 intmsk bit description initial state int_adc [31] 1 = service available, 0 = masked 0 int_usb [30] 1 = service available, 0 = masked 0 int_mstick [29] 1 = service available, 0 = masked 0 reserved [28] not used 0 int_iic [27] 1 = service available, 0 = masked 0 int_spi [26] 1 = service available, 0 = masked 0 int_lcd [25] 1 = service available, 0 = masked 0 reserved [24] not used 0 int_spdif [23] 1 = service available, 0 = masked 0 int_uart0 [22] 1 = service available, 0 = masked 0 reserved [21] not used 0 reserved [20] not used 0 reserved [19] not used 0 reserved [18] not used 0 reserved [17] not used 0 reserved [16] not used 0 reserved [15] not used 0 int_miu [14] 1 = service available, 0 = masked 0 reserved [13] not used 0 int_pri_rtc [12] 1 = service available, 0 = masked 0 int_alarm_rtc [11] 1 = service available, 0 = masked 0 int_dma [10] 1 = service available, 0 = masked 0 reserved [9] not used 0 int_timer c [8] 1 = service available, 0 = masked 0 reserved [7] not used 0
icu preliminary specification S5L840Fx flash type mp3 decoder 30-10 int_wdt [6] 1 = service available, 0 = masked 0 int_timer a [5] 1 = service available, 0 = masked 0 eintg [4] 1 = service available, 0 = masked 0 dbg_wakeup [3] 1 = service available, 0 = masked 1 eint2 [2] 1 = service available, 0 = masked 0 eint1 [1] 1 = service available, 0 = masked 0 eint0 [0] 1 = service available, 0 = masked 0 priority register (priority) register address r/w description reset value priority 0x39c0_000c w irq prio rity control register 0x7f priority bit description initial state arb_sel6 [20:19] arbiter 6 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel5 [18:17] arbiter 5 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_sel4 [16:15] arbiter 4 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel3 [14:13] arbiter 3 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel2 [12:11] arbiter 2 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel1 [10:9] arbiter 1 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel0 [8:7] arbiter 0 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_mode6 [6] arbiter 6 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode5 [5] arbiter 5 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode4 [4] arbiter 4 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode3 [3] arbiter 3 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1
icu preliminary specification S5L840Fx flash type mp3 decoder 30-11 arb_mode2 [2] arbiter 2 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode1 [1] arbiter 1 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode0 [0] arbiter 0 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 interrupt pending register (intpnd) each of the 32 bits in the interrupt pending register shows whether the co rresponding interrupt request is the highest priority one that is unmasked and waits for the inte rrupt to be serviced. since intpnd is located after the priority logic, only one bit can be set to 1 at most, and that is the very interrupt request generating irq to cpu. in interrupt service routine for irq, you can read this regi ster to determine the interrupt source to be serviced among 32 sources. like the srcpnd, this register has to be cleared in the interrupt service routine after clearing srcpnd register. we can clear a specific bit of intpnd register by writing a data to this register. it clears only the bit positions of intpnd corresponding to those set to one in the data. the bi t positions corresponding to those that are set to 0 in the data remains as they are with no change. register address r/w description reset value intpnd 0x39c0_0010 r/w indicates the interrupt request status. 0 = the interrupt has not been requested 1 = the interrupt source has asserted the interrupt request 0x00000000 note : if the fiq mode interrupt is occurred, the corresponding bit of intpnd will not be turned on. because the intpnd register is available only for irq mode interrupt. intpnd bit description initial state int_adc [31] 0 = not request ed, 1 = requested 0 int_usb [30] 0 = not request ed, 1 = requested 0 int_mstick [29] 0 = not reques ted, 1 = requested 0 reserved [28] not used 0 int_iic [27] 0 = not request ed, 1 = requested 0 int_spi [26] 0 = not request ed, 1 = requested 0 int_lcd [25] 0 = not request ed, 1 = requested 0 reserved [24] not used 0 int_spdif [23] 0 = not request ed, 1 = requested 0
icu preliminary specification S5L840Fx flash type mp3 decoder 30-12 int_uart0 [22] 0 = not request ed, 1 = requested 0 reserved [21] not used 0 reserved [20] not used 0 reserved [19] not used 0 reserved [18] not used 0 reserved [17] not used 0 reserved [16] not used 0 reserved [15] not used 0 int_miu [14] 0 = not request ed, 1 = requested 0 reserved [13] not used 0 int_pri_rtc [12] 0 = not reques ted, 1 = requested 0 int_alarm_rtc [11] 0 = not reques ted, 1 = requested 0 int_dma [10] 0 = not request ed, 1 = requested 0 reserved [9] not used 0 int_timer c [8] 0 = not requested, 1 = requested 0 reserved [7] not used 0 int_wdt [6] 0 = not requested, 1 = requested 0 int_timer a [5] 0 = not requested, 1 = requested 0 eintg [4] 0 = not requested, 1 = requested 0 dbg_wakeup [3] 0 = not requested, 1 = requested 0 eint2 [2] 0 = not requested, 1 = requested 0 eint1 [1] 0 = not requested, 1 = requested 0 eint0 [0] 0 = not requested, 1 = requested 0 interrupt offset register (intoffset) the number in the interrupt offset register shows which in terrupt request of irq mode is in the intpnd register. this bit can be cleared automatically by clearing srcpnd and intpnd. register address r/w description reset value intoffset 0x39c0_0014 r indicates the irq interrupt request source 0x00000000 int source the offset value int source the offset value int_adc 31 reserved 15 int_usb 30 int_miu 14 int_mstick 29 reserved 13 reserved 28 int_pri_rtc 12 int_iic 27 int_alarm_rtc 11 int_spi 26 int_dma 10 int_lcd 25 reserved 9
icu preliminary specification S5L840Fx flash type mp3 decoder 30-13 reserved 24 int_timer c 8 int_spdif 23 reserved 7 int_uart0 22 int_wdt 6 reserved 21 int_timer a 5 reserved 20 eintg 4 reserved 19 dbg_wakeup 3 reserved 18 eint2 2 reserved 17 eint1 1 reserved 16 eint0 0 note : if the fiq mode interrupt is occurred, the intoffset w ill not be affected. because t he intoffset register is available only for irq mode interrupt. external interrupt polari ty selection register register address r/w description reset value eintpol 0x39c0_0018 r/w indicates ex ternal interrupt polarity 0x00000000 intpnd bit description initial state external interrupt 7 [7] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 6 [6] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 5 [5] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 4 [4] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 3 [3] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 2 [2] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 1 [1] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt 0 [0] 0 = falling edge interrupt, 1 = rising edge interrupt 0 external interrupt pending register register address r/w description reset value eintpend 0x39c0_001c r/w indicates whether external interrupts are pending. 0x00000000 intpnd bit description initial state external interrupt 7 [7] 0 = no interrupt request pending, 1 = interrupt request pending 0
icu preliminary specification S5L840Fx flash type mp3 decoder 30-14 external interrupt 6 [6] 0 = no interrupt request pending, 1 = interrupt request pending 0 external interrupt 5 [5] 0 = no interrupt request pending, 1 = interrupt request pending 0 external interrupt 4 [4] 0 = no interrupt request pending, 1 = interrupt request pending 0 external interrupt 3 [3] 0 = no interrupt request pending, 1 = interrupt request pending 0 reserved [2] not used 0 reserved [1] not used 0 reserved [0] not used 0 external interrupt mask register register address r/w description reset value eintmsk 0x39c0_0020 r/w indicates whether external interrupts are masked 0x00000000 intpnd bit description initial state external interrupt 7 [7] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 6 [6] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 5 [5] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 4 [4] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 3 [3] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 2 [2] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 1 [1] 0 = external interrupt disable 1 = external interrupt enable 0 external interrupt 0 [0] 0 = external interrupt disable 1 = external interrupt enable 0
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 1/8 ??? miu (memory interface unit) user?s mamual rev0.0 kim, hye-ryeong media plyer p/j system lsi business device solution network division samsung electronics
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 2/8 ??? 2.16.1 functional description features miu supports rom interface, sram interfaces and nor fl ash memory device interfaces. main features of miu are as followings. - supports 1 rom access areas and 1 sram access areas. each rom and sram access areas have 32mbyte address space respectively. - supports 8/16/32bit access to sram and rom. - supports 4mbit(512kbyte) nor flash memory. - supports 8/16/32bit access in no r flash memory read operation. but, only 32bit access is allowed in write operation. - not supports burst mode. only single transfer is supported. memory configuration of S5L840Fx

shows overall addres s configuration in S5L840Fx.

shows memory mapped io configuration of sfrs area in S5L840Fx.
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 3/8 ??? : physical memory area reserved area3 reserved area2 available area 0x0000_0000 0x4000_0000 0x3fff_ffff 0x8000_0000 0x7fff_ffff 0xc000_0000 0xbfff_ffff 0xffff_ffff reserved area1 sfrs(ahb/apb) 0x3fff_ffff 0x3800_0000 reserved area 0x3000_0000 0x2800_0000 0x2000_1000 0x2400_0000 0x2408_0000 0x2801_8000 0x2c00_0000 0x2e00_0000 sram (96k) nor flash (512k) boot rom (4k) 0x0000_0000 reserved area reserved area reserved area reserved area reserved area 0x2000_0000 0x1fff_ffff reserved area : physical memory area : physical memory area reserved area3 reserved area2 available area 0x0000_0000 0x4000_0000 0x3fff_ffff 0x8000_0000 0x7fff_ffff 0xc000_0000 0xbfff_ffff 0xffff_ffff reserved area1 reserved area3 reserved area2 available area 0x0000_0000 0x4000_0000 0x3fff_ffff 0x8000_0000 0x7fff_ffff 0xc000_0000 0xbfff_ffff 0xffff_ffff reserved area1 sfrs(ahb/apb) 0x3fff_ffff 0x3800_0000 reserved area 0x3000_0000 0x2800_0000 0x2000_1000 0x2400_0000 0x2408_0000 0x2801_8000 0x2c00_0000 0x2e00_0000 sram (96k) nor flash (512k) boot rom (4k) 0x0000_0000 reserved area reserved area reserved area reserved area reserved area 0x2000_0000 0x1fff_ffff reserved area sfrs(ahb/apb) 0x3fff_ffff 0x3800_0000 reserved area 0x3000_0000 0x2800_0000 0x2000_1000 0x2400_0000 0x2408_0000 0x2801_8000 0x2c00_0000 0x2e00_0000 sram (96k) nor flash (512k) boot rom (4k) 0x0000_0000 reserved area reserved area reserved area reserved area reserved area 0x2000_0000 0x1fff_ffff reserved area

overall address configuration
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 4/8 ??? apb bridge 0x3c00_0000 0x3c50_0000 0x3c60_0000 0x3c70_0000 0x3c80_0000 0x3c90_0000 0x3ca0_0000 0x3cb0_0000 0x3cc0_0000 0x3cd0_0000 0x3ce0_0000 0x3cf0_0000 0x3d00_0000 0x3d10_0000 timer wdt iic iis in iis out uart spi adc gpio 0x3c10_0000 0x3c20_0000 spdif 0x3c30_0000 usb 0x3c40_0000 lcd i/f sm card mm card sd card clock_gen mem stick 0x3fff_ffff 0x3800_0000 sfrs (apb) 0x3c00_0000 0x3bff_ffff sfrs (ahb) 0x3fff_ffff 0x3800_0000 sfrs (apb) 64m 0x3c00_0000 0x3bff_ffff sfrs (ahb) 64m miu io dma adm unused 0x3800_0000 0x3820_0000 0x3840_0000 reserved icu 0x39c0_0000 reserved 0x39e0_0000 reserved apb bridge 0x3c00_0000 0x3c50_0000 0x3c60_0000 0x3c70_0000 0x3c80_0000 0x3c90_0000 0x3ca0_0000 0x3cb0_0000 0x3cc0_0000 0x3cd0_0000 0x3ce0_0000 0x3cf0_0000 0x3d00_0000 0x3d10_0000 timer wdt iic iis in iis out uart spi adc gpio 0x3c10_0000 0x3c20_0000 spdif 0x3c30_0000 usb 0x3c40_0000 lcd i/f sm card mm card sd card clock_gen mem stick 0x3fff_ffff 0x3800_0000 sfrs (apb) 0x3c00_0000 0x3bff_ffff sfrs (ahb) 0x3fff_ffff 0x3800_0000 sfrs (apb) 64m 0x3c00_0000 0x3bff_ffff sfrs (ahb) 64m miu io dma adm unused 0x3800_0000 0x3820_0000 0x3840_0000 reserved icu 0x39c0_0000 reserved 0x39e0_0000 reserved

memory mapped io configuration
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 5/8 ??? sram/rom controller register map static(rom/sram) memory access parameter registers register address r/w description width miurpara 14~17h r/w rom parameter register 32 bits miuspara 18~1bh r/w sram par ameter register 32 bits bits field description reset value [31:24] - don?t use. these bits appear as zero when read. - [23:20] t acs address set-up time before chip select 1h [19:16] t cos chip select set-up time before output enable 1h [15:8] t acc access cycles. this field must not be zero. otherwise, the result of access is unpredictable. 03h [7:4] t och chip select hold time after output enable 1h [3:0] t cah address hold time after chip select 1h * recommend : t cos , t och cycle is recommended to keep up more than one cycle time. otherwise, it makes a problem at memory read cycle if you adopt a synchronous sram. *the unit of miurpara and miuspa ra fields is clock cycle. c s n o e n / w e n adr t acs t cos t acc t och t cah ck parameter diagram
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 6/8 ??? static(rom/sram) memory size parameter registers register address r/w description width miussize 1c~1fh w static memo ry size pre-setting 32 bits bits field description reset value [31:24] size3 static memory 3 si ze (reserved in S5L840Fx) 00h [23:16] size2 static memory 2 size (sram area in S5L840Fx) 80h [15:8] size1 static memory 1 size (nor flash in S5L840Fx) 40h [7:0] size0 static memory 0 size (rom in S5L840Fx) 01h parameter 1step equals 4kbyte of memory size. 00h = reserved 01h = 4kbyte size. ???? 10h = 64kbyte size ???? 80h = 512kbyte size. memory size ? 4kbyte ? ????? , 3kbyte ? ?? ??? 4kbyte ? ?? ??? ?? ???? . access parameter sram/rom controller, access cycle time parameter set. c s n o e n / w e n adr t acs t cos t acc t och t cah ck
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 7/8 ??? if you use synchronous sram using the clock which sa me phase frequency with hclk, you must keep up the t acc and t och for more than one cycle time. minimum data phase cycle time of sram/rom controller is 2cycle. first 1cycle is ?chip select setup cycle time? and second 1cycle is ?access cycle time?. ??? miurpara/miuspara ? ?? 32?h0001_0100 ?? . 2cycle access ? ???? read ? ???? f/f ? ??? ?? ???? bus ? ??? . ?? ?? ???? ?? ??? ???? ???? ?? ??? ?? ??? ??? ? ? ???? 2cycle access ? ??? ?? . ?? ???? parameter ?? 32?h0001_0110(minimum value) ?? ????? f/f ? ?? ???? bus ? ??? ?? access ? 3cycle ?? ????? ?? . access parameter ? setting ?? assemble ? ??? ??? ?? . example . access time parameter setting (3cycle access) ld a8, #rmiubase //minimum cycle time parameter ld r0, #0001h ld r1, #0110h ldw @[a8+rmiuspara_h], r0 ldw @[a8+rmiuspara_l], r1 //sram parameter set ldw @[a8+rmiurpara_h], r0 ldw @[a8+rmiurpara_l], r1 //rom parameter set.
miu preliminary specification rev0.0 S5L840Fx flash type mp3 decoder march 28, 2003 8/8 ??? size parameter & interrupt : S5L840Fx physical memory area sfrs(ahb/apb) 0x3fff_ffff 0x3800_0000 reserved area 0x3000_0000 0x2800_0000 0x2000_1000 0x2400_0000 0x2408_0000 0x2801_8000 0x2c00_0000 sram (76k) nor flash (256k) boot rom (4k) 0x0000_0000 reserved area reserved area reserved area reserved area 0x2000_0000 0 x1fff_ffff sfrs(ahb/apb) sram nor flash (4k) 0x0000_0000 reserved area reserved area reserved area sfrs(ahb/apb) sram nor flash (4k) 0x0000_0000 reserved area reserved area reserved area reserved area reserved area 0x3000_0000 0x2800_0000 0x2000_1000 0x2400_0000 0x2408_0000 0x2801_8000 0x2c00_0000 sram (76k) nor flash (256k) boot rom (4k) reserved area reserved area 0x2000_0000 sram nor flash (4k) sram nor flash (4k) reserved area out of range out of range out of range out of range 512kb 512kb 512kb 512kb S5L840Fx out-of-range interrupt diagram from miu miu ? out-of-range signal ? 4 ?? sram-like ??? ???? ???? . user ? miussize ? ?? ??? ?? ??? ??? ??? access ??? ? toggle ?? . ? sram-like ??? size ? miussize register ? 8 ???? ???? ??? , out-of-range ??? address ?? ??? register ? ??? ?? ?????? ??? ?? . ? ??? ??? ?? ??? maximum address size ? 8?h80(512kbyte) ? miussize ? ?? ??? write ? ?? . miussize register ? write ? ??? 32bit ??? update ??? ?? ??? ?? ??? ???? ??? ???? ?? . reset ? miussze ? default ?? 32?h0080_8001 ?? .
S5L840F (preliminary spec) iodma 8-1 9 iodma controller overview S5L840F supports four-channel iodma (i/o direct memory access) controller that per forms data transfer without core intervention. each channel of dma controller has two data transfer directions, which are memory-to-io and io-to-memory. in other words, each c hannel can handle the following data transfers: 1. source is in the system bus (ahb) while destination is in the peripheral bus (apb) (ex, memory to an i/o device transfer) 2. source is in the peripheral bus (apb) wh ile destination is in the system bus (ahb) (ex, an i/o device to memory transfer) in iodma, dma is made of repetition of read-and-write and this read-and-write is atomic and is called as a single transfer. a single transfer is a minimum indivisible unit of dma?s. the dma operation can be requested by either softw are or hardware including external dma source.
iodma S5L840F (preliminary spec) 9-2 single transfer protocol there are 2 signals for dma protocol between iodma controller and an io peripheral. signal name in/out description dma_req_n in low-active single transfer request signal. dma_ack_n out low-active single transfer acknowledge signal. the following fsm(finite state machine) is a re commended fsm for io peripheral supporting for iodma. idle req trans ~ackn (need of st) & ackn ackn ~(need of st) & ackn (need of st) state reqn idle req trans 1'b1 1'b0 1'b1 st : single transfer ~ackn figure 9-1. fsm for iodma idle. as an initial state, it waits for the dma request. if it comes, go to req state. at this state, dma_ack_n and dma_req_n are high. req. in this state, dma_req_n becomes low and wait for dma_ack_n signal asserted. trans. in this state, the iodm a executes just one single transfer. iodma can execute only one single transfer of 4 channel s at one moment. therefore, arbitration among channels is needed and this arbitration is executed before a si ngle transfer is started. in arbitration, a channel with higher priority will acquire an ownership of iodma for it s single transfer. the priority of each channel is fixed. channel 0 has the highest priority and channel 3 has the lowest priority.
S5L840F (preliminary spec) iodma 9-3 ch0_reqn ch1_reqn ch0_ackn ch1_ackn inter-channel arbitration ahb+ read ahb+ write inter-channel arbitration ahb+ read ahb+ write a single transfer for channel0 a single transfer for channel1 hclk ch0_reqn ch0_ackn inter-channel arbitration ahb+ read ahb+ write a single transfer for channel0 hclk minimum 6 cycles figure 9-2. single data transfer timing
iodma S5L840F (preliminary spec) 9-4 iodma special registers base address registers for each channel register address r/w description width dmabase0 38400000h r/w base address register for channel 0 32 bits dmabase1 38400020h r/w base address register for channel 1 32 bits dmabase2 38400040h r/w base address register for channel 2 32 bits dmabase3 38400060h r/w base address register for channel 3 32 bits bits field description reset value [31:0] ba[31:0] this field is memory base address for dma and is represented in byte addressing with 32bits. this address should be aligned to a data size of a single transfer. 00000000h transfer count registers for each channel register address r/w description width dmatcnt0 38400008h r/w transfer count register for channel 0 32 bits dmatcnt1 38400028h r/w transfer count register for channel 1 32 bits dmatcnt2 38400048h r/w transfer count register for channel 2 32 bits dmatcnt3 38400068h r/w transfer count register for channel 3 32 bits bits field description reset value [31:20] - this field is reserved and appears as zero when read. ? [19:0] tcnt[19:0] this field is total number of single transfers. xxxxxh
S5L840F (preliminary spec) iodma 9-5 current memory access address registers for each channel register address r/w description width dmacaddr0 3840000ch r current memory address register for channel 0 32 bits dmacaddr1 3840002ch r current memory address register for channel 1 32 bits dmacaddr2 3840004ch r current memory address register for channel 2 32 bits dmacaddr3 3840006ch r current memory address register for channel 3 32 bits bits field description reset value [31:0] caddr[31:0] this field is a current memory access address of dma and is represented in byte addressing with 32bits. xxxxxxxxh configuration registers for each channel register address r/w description width dmacon0 38400004h r/w configuration register for channel 0 32 bits dmacon1 38400024h r/w configuration register for channel 1 32 bits dmacon2 38400044h r/w configuration register for channel 2 32 bits dmacon3 38400064h r/w configuration register for channel 3 32 bits bits field description reset value [31:30] devsel[1:0] device selection. spdif 3 2 1 0 sel ch iis in lcd iis out 00 lcd lcd sdc uart0 out 11 spi out spi in ms lcd 10 usb ch3 usb ch2 usb ch1 01 sm xxb [29] dir dma direction 0 : io to memory dma, 1 : memory to io dma xb [28] addrcon memory address control bit. this bit has to be ?0? this field indicates how to determine memory access address for next single transfer. 0 normal mode. the relationship of next memory access address (naddr) with current memory access address (caddr) is naddr = caddr + 1 * size_of(st 3 ). xb
iodma S5L840F (preliminary spec) 9-6 (continued) 0x2047_0000 bits field description reset value [27:24] schcnt[3:0] sub-channel count. note that channel0, channel 1, channel 2 and channel 3 should have 0 or 1 in this field. in other words, channel 1, channel 2 and channel 3 cannot have more than 2 sub-channels. otherwise, the result is unpredictable. xxxxb [23:22] dsize[1:0] data size. 00 : byte, 01 : half word, 10 : word, 11 : reserved xxb [21:19] blen[2:0] burst length (bl). 000 : (bl = 1), 001 : (bl = 2), 010 : (bl = 3), 011 : (bl = 4), 100 : (bl = 5), 101 : (bl = 6), 110 : (bl = 7), 111 : (bl = 8) xxxb [18] reload reload enable. if ?1?, after whole completion of dma, channel controller automatically restart the same dma without commands. xb [17] hcomint half completion interrupt enable. if ?1?, channel controller make interrupt to inform core on half completion of dma. this is used for double buffering. half completion is checked with following inequality. (dmastatx[19:0] >= dmatcntx[19:1]) xb [16] wcomint whole completion interrupt enable. if ?1?, channel controller inform core on the completion of dma by interrupt. xb [15:0] offset[15:0] offset value. this fi eld is used to calculating next memory access address in subchannel mode. xxxxh
S5L840F (preliminary spec) iodma 9-7 current transfer count re gisters for each channel register address r/w description width dmactcnt0 38400010h r current transfer c ount register for channel 0 32 bits dmactcnt1 38400030h r current transfer c ount register for channel 1 32 bits dmactcnt2 38400050h r current transfer c ount register for channel 2 32 bits dmactcnt3 38400070h r current transfer c ount register for channel 3 32 bits bits field description reset value [31:20] ? this field is reserved and appears as zero when read. ? [19:0] ctcnt[19:0] this field show s the number of single transfer to be remained for whole dma transfer. xxxxxh note: normally, completion of single transfer decreases ctcnt by 1. channel command registers register address r/w description width dmacom0 38400014h w channel 0 command register 32 bits dmacom1 38400034h w channel 1 command register 32 bits dmacom2 38400054h w channel 2 command register 32 bits dmacom3 38400074h w channel 3 command register 32 bits bits field description reset value [31:3] ? this field is reserved and appears as zero when read. ? [2:0] com[2:0] 000 ? 001 : no operation 010 : hold command 011 : skip command * hold command and skip command is only for channel 0. other channels cons ider these commands as no operations. 100 : dma channel on 101 : dma channel off 110 : clear half completion state bit 111 : clear whole completion state bit and half completion state bit. 000b
iodma S5L840F (preliminary spec) 9-8 channel 0 offset2 register register address r/w description width dmanoff0 38400018h r/w channel 0 offset2 register 32 bits bits field description reset value [31:16] ? this field is reserved and appears as zero when read. ? [15:0] off2ch0[15:0] offset2 value. th is field is used for calculating next memory access address in multi-subchannel mode.(not used) xxxxh note: this register is for channel 0 and the other channels do not hav e offset2 register. all channel status register register address r/w description width dmaallst 38400100h r all channel status register 32 bits bits field description reset value [31:15] ? this field is reserved and appears as zero when read. ? [14] dmabusy3 channel 3 dma busy. 0b [13] hcom3 half completion. 0b [12] wcom3 whole completion. 0b [11] ? this field is reserved and appears as zero when read. ? [10] dmabusy2 channel 2 dma busy. 0b [9] hcom2 half completion. 0b [8] wcom2 whole completion. 0b [7] ? this field is reserved and appears as zero when read. ? [6] dmabusy1 channel 1 dma busy. 0b [5] hcom1 half completion. 0b [4] wcom1 whole completion. 0b [3] hold_skip channel 0 when 1, this field indicates that hold or skip command is executing and is not completed. 0b [2] dmabusy0 dma busy. 0b [1] hcom0 half completion. 0b [0] wcom0 whole completion. 0b note: this register is for observing all dm a channels by just a single word read.
chapter 10. wdt module watchdog timer does two main functions: watchdog function and start signal generation after main clock oscillation stabilization. watchdog function is for a situation where the system goes to in abnormal state. in this situation, if the system cannot clear the counter in the watc hdog timer, the counter will count up to overflow and generate a reset signal to initialize all the system. so normal system should periodically clear the counter in the watchdog timer. the second function of the watchdog timer is oscillation stabilizati on. when the system power is on, the main clock from the pll is not stable signal. so the system should wait until this main clock is stabilized. waiting for an enough time to stabilize the main clock, watchdog timer generates the start signal that will start all the system. features - periodic interrupt generation - global reset generation by watchdog timer - start signal generation fo r oscillation stabilization - 8-bits enable/disable register block diagram watchdog timer consists of internal clock divide r, pre-scaler and internal counter. the clock divider divides the main clock with pre-defined divisors which are 2048, 1024, 256, and 128. the divided clocks are selected by the wdt_cs flag in the control register and pre-scaled again by 4- bits pre-scaler. the clock generated from the pre-scaler is supported to the internal 11-bits counter that will generate start signal, reset signal, and interrupt signal. 11-bits counter (wdt_cnt) 4-bits wdt_pre count clock reset after 128 count clocks wdt_int wdt_en wdt_int_en wdt_cs mux after 2048 count clocks clock divider pclk / 2048 pclk / 1024 pclk / 256 pclk / 128 pclk after 64 count clocks one cycle hclk_pre one cycle hclk_pre start_hclk figure 1. watch-dog timer block diagram
S5L840F watchdog timer 2 pin description pin name width i/o description clk 1 i global clock reset_n 1 i global reset apb interface psel 1 i selection in apb penable 1 i enable in apb pwrite 1 i write/read in apb paddr 3 i address in apb pwdata 32 i write data in apb prdata 32 o read data in apb control signals st_mode 1 i scan test mode wdt_stop 1 i stop the function of the watchdog timer wdt_int 1 o basic timer interrupt wdt_start 1 o basic timer start signal for oscillation stabilization wdt_reset 1 o watch-dog timer reset signal wdt_fast 1 i simulation option signal for wdt output signals wdt_noreset 1 i simulation option signal for disabling wdt_reset wdt_start_hclk 1 o hclk one cycle signal of wdt_start clk main clock. the clock after the power-on is 27 mhz directed from the pll. in normal operation, apb clock is supported. reset_n global reset to reset the internal register apb interface signals (psel, penable, pwrite, paddr, pwdata, prdata) amba apb interface signals st_mode scan test mode signal. in scan test mode, the in ternally generated or gated clocks are disabled and the main clock is used for all the internal flip -flops. this signal is used the selection signal for the clock muxing. wdt_stop watchdog timer stop signal. in debugging mode, the watchdog timer should not operate as normal. the wdt_stop signal is used to temporarily stop the watchdog timer function. wdt_int watchdog timer interrupt signal. when the interrupt operation is enabled, the interrupt signal is generated periodically. the time can be adjusted by the wdt_cs and wdt_pre values. wdt_start start signal. this signal will be long enough to stabilize the clock from the pll after the power-on. after the stabilization of the clock, the reset signal s of all the other modules are released and they start the normal operation. wdt_reset
S5L840F watchdog timer 3 when the chip goes into abnormal state, it will not execute the normal operation. in this case, the normal clear operation for the watchdog timer may not be executed. when the watchdog timer is not cleared periodically, the reset signal is generated that will reset all the chip to go into the power-on state. wdt_fast for fast simulation, it makes wdt_start, wdt_int, wdt_reset to be generated at more short time than normal operations. wdt_noreset for long time simulation, it sets wdt global reset(wdt_reset) to zero wdt_start_hclk this signal is hclk_pre one cycle signal of wdt_start. registers name width address(virtual) r/w description reset wdtcon 32 0x3c80 0000(0x39 0000) r/w control register 0x0000 0000 wdtcnt 32 0x3c80 0000(0x39 0004) r/w 11-bits internal counter 0x0000 0000 wdtcon name width address r/w description reset wdtcon 32 0x3c80 0000(0x39 0000) r/w control register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wdt_pre 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdt_cs wdt_clr wdt_en bits name type description 19:16 wdt_pre r/w pre-scale value 15 wdt_int_en r/w enable or disable the periodic interrupt generation when watchdog timer is enabled. 0 1 disable the periodic interrupt generation enable the periodic interrupt generation 14:12 wdt_cs r/w clock selection 3?b100 3?b001 3?b010 3?b011 3?b000 pclk / 2048 pclk / 1024 pclk / 256 pclk / 128 pclk / 8 11:8 wdt_clr w clear the internal 11-bits counter register. as this field is write-only, the read value is always zero. 4?b1010 others clear the internal 11-bits counter register nothing 7:0 wdt_en r/w enable the watch-dog timer 8?b10100101 others disable the reset/start signal generation by the watchdog timer. nothing
S5L840F watchdog timer 4 wdtcnt name width address r/w description reset wdtcnt 32 0x3c80 0000(0x39 0004) r 11-bits internal counter 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 wdt_cnt bits name type description 10:0 wdt_cnt r 11-bits internal counter
S5L840F watchdog timer 5 prescaling system clock is scaled in two stages: wdt_pre and wdt_cs. the wdt_cs has 8 types of pre- scale value and the wdt_pre has a 4-bits resolution for pre-scaling. when the power is on, the clock generated from the pll is not clean signal that should not be used for the operation of the chip. it takes 3 ~ 4 ms to stabilize the pll. the watchdog timer in S5L840F waits for 4.85 ms after its reset is relea sed. the start signal will tr igger the release of the all the other reset signals when the clock from the pll is stabilized enough. when the watchdog timer interrupt is enabled, periodic interrupt sign al is generated that will be used to clear the watchdog counter. when the chip falls to abnormal state, it should be reset. when the watchdog timer is not cleared and counts up to overflow, it generates the reset si gnal and reset the chip. the time is defined by the wdt_cs and wdt_pre as shown in t able 1, table 2, table 3 and table4. wdt_pre = 0 wdt_start (x64) wdt_int (x128) wdt_reset (x2048) wdt_cs frequency/ period frequency/ period frequency/ period frequency/ period frequency/ period 13.18 khz 13.18 khz 0.21 khz 0.10 khz 6.44 hz pclk / 2048 75.85 us 75.85 us 4.85 ms 9.71 ms 155.34 ms 26.37 khz 26.37 khz 0.41 khz 0.21 khz 12.87 hz pclk / 1024 37.93 us 37.93 us 2.43 ms 4.85 ms 77.67 ms 105.47 khz 105.47 khz 1.65 khz 0.82 khz 51.50 hz pclk / 256 9.48 us 9.48 us 0.61 ms 1.21 ms 19.42 ms 210.94 khz 210.94 khz 3.30 khz 1.65 khz 103.00 hz pclk / 128 4.74 us 4.74 us 0.30 ms 0.61 ms 9.71 ms 3.375mhz 3,375mhz 52,73khz 26,37khz 1,65khz pclk / 8 296.3 ms 296.3ms 18.96us 37.93us 606.81us table 1. pre-scaled clock frequency and periods when wdt_pre = 0 and pclk = 27 mhz wdt_pre = 15 wdt_start (x64) wdt_int (x128) wdt_reset (x2048) wdt_cs frequency/ period frequency/ period frequency/ period frequency/ period frequency/ period 13.18 khz 0.82 khz 12.87 khz 6.44 khz 0.40 hz pclk / 2048 75.85 us 1,213.63 us 77.67 ms 155.34 ms 2,485.51 ms 26.37 khz 1.65 khz 25.75 khz 12.87 khz 0.80 hz pclk / 1024 37.93 us 606.81 us 38.84 ms 77.67 ms 1,242.76 ms 105.47 khz 6.59 khz 103.00 khz 51.50 khz 3.22 hz pclk / 256 9.48 us 151.70 us 9.71 ms 19.42 ms 310.69 ms 210.94 khz 13.18 khz 205.99 khz 103.00 khz 6.44 hz pclk / 128 4.74 us 75.85 us 4.85 ms 9.71 ms 155.34 ms 3.375mhz 0.21mhz 3.296khz 1.648khz 102.99hz pclk / 8 296.3 ms 5.037us 322.37us 644.74us 10.3ms table 2. pre-scaled clock frequency and periods when wdt_pre = 15 and pclk = 27 mhz
S5L840F watchdog timer 6 wdt_pre = 0 wdt_start (x64) wdt_int (x128) wdt_reset (x2048) wdt_cs frequency/ period frequency/ period frequency/ period frequency/ period frequency/ period 16hz 16hz 0.25 hz 0.125 hz 0.00781hz pclk / 2048 62.5ms 62.5ms 4s 8s 128s 32hz 32hz 0.5hz 0.25 hz 0.0156hz pclk / 1024 31.25ms 31.25ms 2s 4s 64s 128hz 128hz 2hz 1hz 0.0625hz pclk / 256 7.81ms 7.81ms 0.5s 1s 16s 256hz 256hz 4hz 2hz 0.125hz pclk / 128 3.906ms 3.906ms 0.25s 0.5s 8s 4096hz 4096hz 64hz 32hz 2hz pclk / 8* 244.14us 244.14us 15.63ms 31.25ms 0.5s *pclk/8 mode is default after reset table 3. pre-scaled clock frequency and periods when wdt_pre = 0 and pclk = 32,768hz wdt_pre = 15 wdt_start (x64) wdt_int (x128) wdt_reset (x2048) wdt_cs frequency/ period frequency/ period frequency/ period frequency/ period frequency/ period 16hz 1hz 0.0156 hz 0.00781 hz 0.00048hz pclk / 2048 62.5ms 1s 64s 128s 2048s 32hz 2hz 0.03125hz 0.0156 hz 0.000976hz pclk / 1024 31.25ms 0.5s 32s 64s 1024s 128hz 8hz 0.125hz 0.0625hz 0.0039hz pclk / 256 7.81ms 125ms 8s 16s 256s 256hz 16hz 0.25hz 0.125hz 0.00781hz pclk / 128 3.906ms 62.5ms 45s 8s 128s 4096hz 256hz 4hz 2hz 0.125hz pclk / 8 244.14us 3.906ms 0.25s 0.5ms 8s table 4. pre-scaled clock frequency and periods when wdt_pre = 15 and pclk = 32,768hz simulation mode we add simulation mode for fast and stable simulation and add two signals to wdt module. wdt_fatst, wdt_noreset are these signals. if wdt_ fast is set to high, wdt module output signals ( wdt_start, wdt_int, wdt_reset) occurred more fr equently than normal. and wdt_noreset is set to high, wdt module don?t generation wdt_reset. in si mulation mode, these two signals are all high. to go to simulation mode, see chapter of mode control part.
chapter 11. rtc module the real time clock (rtc) unit can operate by the backup battery although the system power turns off. the rtc transmits data to cpu as bcd (binary coded decimal) values. the data include second, minute, hour, date, day of the week, month, and year. the rtc unit works with an external 32.768khz crystal and also can perfo rm the alarm function. the block diagram is shown in figure 1. features ? 2 data transfer modes ? transmission, reception ? clock and calendar functions (bcd display) : seconds, minutes, hours, date, day of week, month, year ? leap year generator ? wake-up (pmwkup) signal generation: support on the power down mode ? alarm interrupt (almint) in normal operation mode ? cyclic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16second, 1/4 second, 1/2 second, or 1 second ? round reset function: 30-, 40-, 50-second ? current consumption: 3.5 a (typical) ? operation temperature range: 0 c ~ 70 c
S5L840F watchdog timer 2 alarm generator hour control register & control oscillator and clock divider leap year generator reset register date day mon year sec min rtc internal module bus apb interface amba apb(advanced peripheral bus) rtc pwdn pmwkup almint rtcextal1 rtcxtal1 rtcosc pri figure 1. top block diagram pin description the signals of real time clock are divided into three sets. the first set includes the apb signals to configure the control registers. another is to handshake with the power management block while in power down mode and relating to interrupt controller. the final is a related crystal signal that will be applied to off- chip crystal. table 1-1a. apb interface signals name type source/ destination description pclk in amba apb apb bus clock. presetn in amba apb active low. global reset signal. penable in amba apb apb enable signal. pselptc in amba apb apb selection signal. pwrite in amba apb apb read write signal. paddr[7:0] in amba apb apb address bus. table 1-1b. apb interface signals name type source/ destination description pwdata[15:0] in amba apb apb write data bus. prdata[15:0] out amba apb apb read data bus.
S5L840F watchdog timer 3 table 1-2. power management and interrupt controller interface signals name type source/ destination description pwdn in power management when this signal is high, rtc is operated by backup battery. pmwkup out power management this signal is to wake up the power management. while power down mode, this signal can be used to wake up power management unit. almint out interrupt controller active high. when not power down mode, alarm enable bit in rtc was set and alarm time is matched by this signal that rtc requests a interrupt to interrupt controller. pri out interrupt controller active high. this signal is to indicate 1/256 second, 1/64 second, 1/16 second, 1/4 second , 1/2 second, or 1 second. table 1-3. crystal interface signals name type source/ destination description rtcextal1 in clkgen unit clo ck from clkgen unit (i_rclk) table 1-4. scan test interface signals name type source/ destination description tms in testmode rtc scan mode selection signal scan_in in testmux scan serial input data scan_en in testmux scan serial data enable scan_out out testmux scan serial output data function description system clock frequency control the leap year generator calculates which the last date of each month is 28,29,30 or 31 that is based on data from bcdday, bcdmon, and bcdyear. this also considers leap years in deciding the last date. a 16 bit counter can just represent four bcd digits, so it can decide whether any year is a leap year or not. system power operation it is required to set bit 1 of the rtccon register for interfacing between cpu and rtc logic. an one second error can occur when the cpu reads or writes data into bcd counters and this can cause the change of the higher time units. when the cpu reads/writes data to/from the bcd counters, another time unit may be changed if bcdsec register is overflowed. to avoid this problem, the cpu should reset bcdsec register to 00h. the reading sequence of the bcd counters is bcdyear, bcdmon, bcddate, bcdday, bcdhour, bcdmin, and bcdsec. it is required to read it again from bcdyear to bcdsec if bcdsec is zero.
S5L840F watchdog timer 4 alarm function the rtc generates alarm signal at specified time in the power down mode or normal operation mode. in normal operation mode, the alarm interrupt (almint) is activated and in the power down mode the power management wake up (pmwkup) signal is activated. the rtc alarm register, rtcalm, determines the alarm enable and the condition of the alarm time setting. note that the pwdn signal determines whether the normal operation or power down mode. round reset function the round reset function can be performed by the rtc round reset register, rtcrst. you can select the round boundary (30, 40, or 50 sec) of the second carry generation and the second value is rounded to zero value in the round reset operation. for example, when the current time is 23:37:47 and the round boundary is selected as 40 sec, the round reset operation changes the current time with 23:38:00. rtc operation initial settings of registers after power-on almost of all registers (except bcd registers) have initial value after the power is turned on. setting the time figure 2. shows how to set the time when clock is stopped. this works when the entire calendar or clock is to be set. stop clock, reset divider circuit start clock set seconds, minutes, hour, date, day of the week, month and year write "1" to clkrst and "1" to startb in the rtccon register order is irrelevant write "0" to startb in the rtccon register to reset the divider circuit and set the counter figure 2. setting the time
S5L840F watchdog timer 5 alarm function figure 3. shows how to use the alarm function. alarms can be generated using the seconds, minutes, hours, day of week, date, month, year or any combination of these. set the almen bit (bit 7) in the register on which the alarm is placed to "1", and then set the alarm time. clear the almen bit in the register on which the alarm is placed to "0". when the intmode bit of rtcim register is high, and the clock and alarm times match, "1" is set in the pend bit of rtcpend register. the detection of alarm can be checked with reading the pend bit. clock running set alarm time set whether to use alam interrupts that are level or edge when using interrupts, the interrupt type bit (intmode) is set or not. bcd clock is running monitor alarm time (wait for interrupt) figure 3. using the alarm function
S5L840F watchdog timer 6 programmer's model register memory map rtc_base : 0x 3d20_0000 ( virtual base address : 0x3a 4000) register address r/w description reset value rtccon base + 0x00 r/w rtc control register 0x00 rtcrst base + 0x04 r/w rtc round reset register 0x00 rtcalm base + 0x08 r/w rtc alarm control register 0x00 almsec base + 0x0c r/w alarm second data register 0x00 almmin base + 0x10 r/w alarm minute data register 0x00 almhour base + 0x14 r/w alarm hour data register 0x00 almdate base + 0x18 r/w alarm date data register 0x00 almday base + 0x1c r/w alarm day of week data register 0x00 almmon base + 0x20 r/w alarm month data register 0x00 almyear base + 0x24 r/w alarm year data register 0x0000 bcdsec base + 0x28 r/w bcd second register - bcdmin base + 0x2c r/w bcd minute register - bcdhour base + 0x30 r/w bcd hour register - bcddate base + 0x34 r/w bcd date register - bcdday base + 0x38 r/w bcd day of week register - bcdmon base + 0x3c r/w bcd month register - bcdyear base + 0x40 r/w bcd year register - rtcim base + 0x44 r/w rtc interrupt mode register 0x00 rtcpend base + 0x48 r/w rtc interrupt pending register 0x00 rtc control register (rtccon) rtccon register consists of 6-bits such as startb that controls to run the normal counters, rtcen that controls the read/write enable of the bcd registers, clksel, cntsel, and clkrst for bcd counters testing. rtcen bit controls all interfaces between the cpu and th e rtc, so it should be set to '1' in an initialization routine to enable data transfer after a system reset. instead of working bcd with 1hz, clksel bit enables the operation of bcd counters with an external clock which is applied through the pin extal1 to the test bcd counters. cntsel bit converts the dependent operation of bcd counters into independent counters for the test. clkrst resets the frequency divided logic in the rtc. oscen bit controls the path from input of crystal to the output of divider logic. if this bit is high, the output of
S5L840F watchdog timer 7 divider is 1 hz clock. to purpose of testing that oscillator circuit and divider block, this bit is implemented. table 1-6. rtc control register (rtccon) rtccon bit description initial state startb [0] rtc start bit 0 : run 1: halt 0 rtcen [1] rtc write enable bit 0 : disable 1: enable 0 clksel [2] bcd counter test clock set bit 0 : extal1 divided clock (1 hz) 1 : reserved (extal1 clock : 32.768 khz) 0 cntsel [3] bcd count test type set bit 0 : merge bcd counters 1: reserved (separate bcd counters) 0 clkrst [4] rtc clock count set bit 0 : no reset 1: reset 0 oscen [5] oscillator and divider circuit test enable bit 0 : disable 1 : enable 0 rtc alarm control register (rtcalm) rtcalm register determines the alarm enable and the condition of the alarm time setting. note that rtcalm register generates the alarm signal through both almint and pmwkup in power down mode, while only almint in normal operation mode. table 1-7a. rtc alarm control register (rtcalm) rtccon bit description initial state secen [0] second alarm enable bit 0 : disable 1 : enable 0 minen [1] minute alarm enable bit 0 : disable 1 : enable 0 houren [2] hour alarm enable bit 0 : disable 1 : enable 0 dateen [3] date alarm enable bit 0 : disable 1 : enable 0 dayen [4] day of week alarm enable bit 0 : disable 1 : enable 0 table 1-7b. rtc alarm control register (rtcalm) rtccon bit description initial state monen [5] month alarm enable bit (reserved bit) for alarm function, this bit should be set. 0 yearen [6] year alarm enable bit (reserved bit) for alarm function, this bit should be set. 0 almen [7] alarm global enable bit 0 : disable 1 : enable 0
S5L840F watchdog timer 8 alarm second data register (almsec) table 1-8. alarm second data register (almsec) almsec bit description initial state secdata [6:0] bcd value for alarm second bits [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 0 reserved [7] 0 alarm minute data register (almmin) table 1-9. alarm minute data register (almmin) almmin bit description initial state mindata [6:0] bcd value for alarm second bits [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 0 reserved [7] 0 alarm hour data register (almhour) table 1-10. alarm hour data register (almhour) almhour bit description initial state hourdata [5:0] bcd value for alarm hour bits [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 2 0 reserved [7:6] 0 alarm date data register (almdate) table 1-11. alarm date data register (almdate) almdate bit description initial state datedata [5:0] bcd value for alarm date, from 0 to 28, 29, 30, 31 (decimal : 01 ~ 31) [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 3 0 reserved [7:6] 0 alarm day of week data register (almday)
S5L840F watchdog timer 9 table 1-12. alarm day of week data register (almday) almday bit description initial state daydata [2:0] bcd value for alarm day bits [2:0] bit is from 0 to 6 000 : sunday 001 : monday 010 : tuesday 011 : wednesday 100 : thursday 101 : friday 110 : saturday 0 reserved [7:3] 0 alarm month data register (almmon) table 1-13. alarm month data register (almmon) almmon bit description initial state mondata [4:0] bcd value for alarm month bits [3:0] bit is from 0 to 9 [4] bit is from 0 to 1 0 reserved [7:5] 0 alarm year data register (almyear) table 1-14. alarm year data register (almyear) almyear bit description initial state yeardata [15:0] bcd value for alarm year bits [7:0] bit is from 0 to 99 [15:8] bit is from 0 to 99 0 rtc round reset register (rtcrst) table 1-15. rtc round reset register (rtcrst) rtcrst bit description initial state seccr [2:0] round boundary for second carry generation bits 011 : over than 30 sec 100 : over than 40 sec 101 : over than 50 sec 0 srsten [3] round second reset enable bit 0 : disable 1 : enable 0 reserved [7:5] 0 bcd second data register (bcdsec) table 1-16. bcd second data register (bcdsec) bcdsec bit description initial state secdata [6:0] bcd value for second bits undef.
S5L840F watchdog timer 10 [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 reserved [7] - bcd minute data register (bcdmin) table 1-17. bcd minute data register (bcdmin) bcdmin bit description initial state mindata [6:0] bcd value for minute bits [3:0] bit is from 0 to 9 [6:4] bit is from 0 to 5 undef. reserved [7] - bcd hour data register (bcdhour) table 1-18. bcd hour data register (bcdhour) bcdhour bit description initial state hourdata [5:0] bcd value for hour bits [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 2 undef. reserved [7:6] - bcd date data register (bcddate) table 1-19. bcd date data register (bcddate) bcddate bit description initial state datedata [5:0] bcd value for da te bits(decimal : 01 ~ 31) [3:0] bit is from 0 to 9 [5:4] bit is from 0 to 3 undef. reserved [7:6] - bcd day of week data register (bcdday) table 1-20. bcd day of week data register (bcdday) bcdday bit description initial state dateday [2:0] bcd value for date bits [2:0] bit is from 0 to 6 000 : sunday 001 : monday 010 : tuesday 011 : wednesday 100 : thursday 101 : friday 110 : saturday undef. reserved [7:3] - bcd month data register (bcdmon)
S5L840F watchdog timer 11 table 1-20. bcd month data register (bcdmon) bcdmon bit description initial state mondata [4:0] bcd value for month bits [3:0] bit is from 0 to 9 [4] bit is from 0 to 1 undef. reserved [7:5] - bcd year data register (bcdyear) table 1-21. bcd year data register (bcdyear) bcdyear bit description initial state yeardata [15:0] bcd value for year bits [7:0] bit is from 0 to 99 [15:8] bit is from 0 to 99 undef. rtc interrupt mode register (rtcim) periodic interrupt mode (peimode): indicates generation of interrupt with the period designated by the pes bits. when set to "1" peimode generates periodic interrupts. table 1-22. rtc interrupt mode register (rtcim) rtcim bit description initial state intmode [1:0] interrupt mode selection bit x0 : disable alarm interrupt mode. x1 : enable alarm interrupt mode. 01 : supports on the edge alarm interrupt. 11 : supports on the level alarm interrupt. 0 peimode [2] periodic interrupt mode bit 0 : interrupts not generated with the period designated by the pes bits. 1 : interrupts generated with the period designated by the pes bits. 0 pes [5:3] these bits specify the periodic interrupt. 000 : no periodic interrupt generated 001 : periodic interrupt generated every 1/256 second 010 : periodic interrupt generated every 1/64 second 011 : periodic interrupt generated every 1/16 second 100 : periodic interrupt generated every 1/4 second 101 : periodic interrupt generated every 1/2 second 110 : periodic interrupt generated every 1 second 111 : reserved 0 reserved [7:6] 0
S5L840F watchdog timer 12 rtc interrupt pending register (rtcpend) table 1-23. rtc interrupt pending register (rtcpend) rtcpend bit description initial state pend [0] interrupt pending enable bit 0 : pend bit is cleared. 1 : pend bit is pending. 0 reserved [7:1] 0 timing diagram interfacing rtc to apb interfacing the rtc to the apb is described in: zf read transfer zf write transfer figure 5. illustrates a read transfer. figure 5. a read transfer pclk t1 t2 t3 t4 t5 pwrite penable paddr[7:0] address 1 prdata pselrtc data 1 data sampled by apb bridge
S5L840F watchdog timer 13 figure 6. illustrates a write transfer. figure 6. a write transfer pclk t1 t2 t3 t4 t5 pwrite penable paddr[7:0] address 1 pwdata pselrtc data 1 rtc registers data 1
chapter 12. timer module S5L840F has internally two timers. they are named as timer a, timer c. timer a has the full function. however, timer c has a limited function that is derived from the full function of timer a. the supported modes of the full functional timer are interval mode, pwm (pulse width modulation) mode, one-shot pwm mode, and capture mode. the full functional timer has internally one counter register (tm_cnt), one pre-scale register (tm_pre), and two data registers (tm_data0, tm_data1). the tm_cnt is incremented by a pre-scaled clock that is pre-scaled by tm_pre val ue from an external clock or internally selected clock. the role of tm_data0 and tm_data1 is different for each mode. the timer with paritial funcion (timer c) does not have the tm_data1 register because of its functional limit. features - four 16-bits timer: timer a, timer c - timer a support interval mode, pwm mode, one-shot mode, and capture mode - timer c support interval mode - pre-scaling the counting clock with th e 10-bits pre-scale register (tm_pre) - 0 ~ 100 % duty ratio pwm signal generation
S5L840F 16 bits timer 2 block diagram buffer register tm_ovf_int 16-bit counter (tm_cnt) 10-bit tm_pre tmcap data register 1 (tm_data1) tm_mat_int1 tm_out tm_mat_int0 m u x overflow buffer mux comparator buffer register data register 0 (tm_data0) comparator edge detector clear capture interrupt capture count clock clock division pclk / 64 pclk / 16 pclk / 4 pclk / 2 extclk1 extclk0 pclk tm_cs figure 1. block diagram for timer a timer a control register timer a compare timer a capture timer a prescaler timer c control register timer c compare timer c prescaler figure 2. timer block diagram pin description pin name width i/o description reset_n 1 i global reset clk 1 i global clock clk_ext0 4 i external clock 0 for internal counting 0 1 2 3 external clock 0 for timer a external clock 0 for timer b external clock 0 for timer c external clock 0 for timer d clk_ext1 4 i external clock 1 for internal counting 0 1 external clock 1 for timer a external clock 1 for timer b
S5L840F 16 bits timer 3 2 3 external clock 1 for timer c external clock 1 for timer d intr 4 o interrupt apb interface psel 1 i apb selection signal penable 1 i apb enable signal pwrite 1 i apb write/read signal paddr 7 i apb address pwdata 32 i apb data input prdata 32 o apb data output external interface cap_port 2 i external signal to be captured pwm_out 2 o pwm signal output pwm_out[0] pwm_out[1] timer a pwm output timer b pwm output reset_n global reset to reset the internal register clk apb clock (main clock) clk_ext0/1 clk_ext0 and clk_ext1 are the external clock ports to count the internal counter. as the divided clock from the main clock mainly counts the internal counter, the counter value may not be accurate for some application. in that case, external accurate clock is used for more accurate counting operation. the positive edge of external clocks is internally detected by the main clock. so the external clock frequency should be lower than the main clock. intr when an interrupt condition occurs, an interrupt request is generated to the cpu core. apb interface signals (psel, penabl e, pwrite, paddr, pwdata, prdata) amba apb interface signals cap_port positive edge or negative edge of external sig nals is detected and the time of these events are captured to the internal data registers. as these cap ports get external signals, they are digitally filtered in the internal capture block with 5 tabs. so glitches within 5 main clock periods in the cap port are digitally filtered out. pwm_out in interval mode and pwm mode, when the value of counter equals to that of data register, a match interrupt occurs and the pwm_out signal is toggled. this port is used to generate the toggling signal in interval mode or pwm signal in pwm mode.
S5L840F 16 bits timer 4 register map name width address(virtual) r/w description reset timer a registers tacon 32 0x3c70 0000(0x38 e000) r/w control register 0x0000 0000 tacmd 32 0x3c70 0004(0x38 e004) r/w command register 0x0000 0000 tadata0 32 0x3c70 0008(0x38 e008) r/w data0 register 0x0000 0000 tadata1 32 0x3c70 000c(0x38 e00c) r/w data1 register 0x0000 0000 tapre 32 0x3c70 0010(0x38 e010) r/w prescale register 0x0000 0000 tacnt 32 0x3c70 0014(0x38 e014) r/w counter register 0x0000 0000 timer c registers tccon 32 0x3c70 0040(0x38 e040) r/w control register 0x0000 0000 tccmd 32 0x3c70 0044(0x38 e044) r/w command register 0x0000 0000 tcdata0 32 0x3c70 0048(0x38 e048) r/w data0 register 0x0000 0000 tcre 32 0x3c70 0050(0x38 e050) r/w prescale register 0x0000 0000 tccnt 32 0x3c70 0054(0x38 e054) r/w counter register 0x0000 0000
S5L840F 16 bits timer 5 timer a registers tacon name width address r/w description reset tacon 32 0x3c70 0000 r/w control register for timer a 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_cs bits name type description 20 ta_out r the pwm output in interval/pwm/one-shot modes 18 ta_ovf r/w overflow interrupt status. although the interrupt is disabled, this field is updated when an overflow interrupt occurs. - writing one clears this flag - writing zero has no effect 17 ta_int1 r/w match interrupt 1 status. although the interrupt is disabled, this field is updated when a match interrupt 1 occurs. - writing one clears this flag - writing zero has no effect 16 ta_int0 r/w match interrupt 0 status. although the interrupt is disabled, this field is updated when a match interrupt 0 occurs. - writing one clears this flag - writing zero has no effect 14 ta_ovf_en r/w enable the overflow interrupt. when disabled, overflow interrupt sets the ta_ovf but it does not generate an interrupt request signal to external interrupt control unit. 0 1 disable the overflow interrupt enable the overflow interrupt 13 ta_int1_en r/w enable the match interrupt 1. when disabled, match interrupt 1 sets the ta_int1 but it does not generate an interrupt request signal to external interrupt control unit. 0 1 disable the overflow interrupt enable the overflow interrupt rising clear clear the co u 12 ta_int0_en r/w enable the match interrupt 0. when disabled, match interrupt 0 sets the ta_int0 but it does not generate an interrupt request signal to external interrupt control unit. 0 1 disable the overflow interrupt enable the overflow interrupt rising clear clear the co u 11 ta_start r/w in interval/pwm/one-shot modes, this field is set to the ta_out by clear operation (writing one to ta_clr). in pwm and one-shot mode, whenever an mat_int1 occurs, this value is also updated to the ta_out. in interval mode, if mat_int0 occurs, this value is updated to the ta_out.
S5L840F 16 bits timer 6 10:8 ta_cs r/w timer clock source selection 3?b000 3?b001 3?b010 3?b011 3?b10x 3?b11x pclk / 2 pclk / 4 pclk / 16 pclk / 64 external clock 0 external clock 1 7 ta_cap_mode r/w in capture mode, 0 1 rising clear mode. clear the counter when a rising edge is detected. falling clear mode. clear the counter when falling edge is detected 5:4 ta_mode_sel r/w operation mode selection 2?b00 2?b01 2?b10 2?b11 interval mode pwm mode one-shot mode capture mode tacmd name width address r/w description reset tacmd 32 0x3c70 0004 r/w command register for timer a 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name type description 1 ta_clr w clear operation. this field is always zero when read. 0 1 nothing occurs initialize the timer. - clear the counter register. - the value of ta_start is set to ta_out. - ta_data0 and ta_data1 are updated to the internal buffers - initialize the state of the previously captured signal. 0 ta_en r/w timer enable command 0 1 disable the timer enable the timer tadata0 name width address r/w description reset tadata0 32 0x3c70 0008 r/w data register 0x0000 0000
S5L840F 16 bits timer 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_data0 bits name type description 15:0 ta_data0 r/w this field is used differently by the operation mode. interval mode the target counting value is stored in this field. when the counter value equals to this register, a mat_int0 interrupt is generated. whenever an mat_int0 occurs or clear operation is executed, this value is updated to the internal data buffer 0. pwm mode/ one-shot mode the target counting value is stored in this field. when the counter value equals to this register, a mat_int0 interrupt is generated. this field is updated to the internal data buffer 0 when mat_int1 occurs or when clear operation is executed. capture mode in rising-edge clear mode, the captured data at the falling edge is stored to this register. in falling-edge clear mode, the captured data at the rising edge is stored to this register. tadata1 name width address r/w description reset tadata1 32 0x3c70 000c r/w data register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_data1 bits name type description 15:0 ta_data1 r/w this field is used differently by the operation mode. interval mode not used pwm mode/ one-shot mode the target counting value is stored in this field. when the counter value equals to this register, a mat_int1 interrupt is
S5L840F 16 bits timer 8 generated. this field is updated to the internal data buffer 1 when mat_int1 occurs or when clear operation is executed. capture mode in rising-edge clear mode, the captured data at the rising edge is stored to this register. in falling-edge clear mode, the captured data at the falling edge is stored to this register. tapre name width address r/w description reset tapre 32 0x3c70 0010 r/w pre-scale register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_pre bits name type description 9:0 ta_pre r/w pre-scale value tacnt name width address r/w description reset tacnt 32 0x3c70 0014 r counter register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ta_cnt bits name type description 15:0 ta_cnt r counter register
S5L840F 16 bits timer 9 timer c registers tccon name width address r/w description reset tccon 32 0x3c70 0040 r/w control register for timer c 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc_cs bits name type description 18 reserved - this flag should be set to 0. 16 tc_int0 r/w match interrupt 0 status - writing one clears this flag - writing zero has no effect 14 reserved - this flag should be set to 0 12 tc_int0_en r/w enable the match interrupt 0. when disabled, match interrupt 0 sets the tc_int0 but it does not generate an interrupt request signal to external interrupt control unit. 0 1 disable the overflow interrupt enable the overflow interrupt rising clear clear the co u 10:8 tc_cs r/w timer clock source selection 3?b000 3?b001 3?b010 3?b011 3?b10x 3?b11x pclk / 2 pclk / 4 pclk / 16 pclk / 64 external clock 0 external clock 1 tccmd name width address r/w description reset tccmd 32 0x3c70 0044 r/w command register for timer c 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name type description
S5L840F 16 bits timer 10 1 tc_clr w initialize the timer 0 1 nothing occurs initialize the timer. - clear the counter register. - tc_data0 is updated to the internal buffers - initialize the state of the previously captured signal. 0 tc_en r/w timer enable command 0 1 disable the timer enable the timer tcdata0 name width address r/w description reset tcdata0 32 0x3c70 0048 r/w data register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc_data0 bits name type description 15:0 tc_data0 r/w this field is used differently by the operation mode. interval mode the target counting value is stored in this field. when the counter value equals to this register, a mat_int0 interrupt is generated. whenever an mat_int0 occurs or clear operation is executed, this value is updated to the internal data buffer 0 for next comparison. tcpre name width address r/w description reset tcpre 32 0x3c70 0050 r/w pre-scale register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc_pre bits name type description 9:0 tc_pre r/w pre-scale value
S5L840F 16 bits timer 11 tccnt name width address r/w description reset tccnt 32 0x3c70 0054 r counter register 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc_cnt bits name type description 15:0 tc_cnt r counter register
S5L840F 16 bits timer 12 interval mode this mode is selected by setting tm_mode_sel to 0b00x. when the (tm_cnt + 1) value equals to the buffer corresponding to tm_data0 in the operation, an interrupt (tm_mat_int0) occurs, the value of the tm_cnt is cleared to zero and tm_cnt counts up again. in this mode, tm_data1 is not used. the tm_out pin of a timer is used to generate a signal that is toggled by tm_mat_int0. the waveform of the signal generated in this mode is in figure 2. as you can see, changing the value of tm_data0 varies the widt h of the pulse. tm_data0 can be updated during the operation but the effect of that value occurs at the next phase. tm_cnt value 0 interrupt (tm_mat_int0) write tm_data0=100 write tm_data0=200 start tm_data0=150 150 100 200 200 fig 2. interval mode operation the detailed waveform is shown in figure 3. pclk counting enable tm_cnt interval mode, tm_data0 = 3, tm_start = 1 tm_out 0000 0001 0002 0000 tm_en tm_clr data0_buf 0003 intr (mat_int0) figure 3. waveform in interval mode pwm (pulse width modulation) mode like the interval mode, the tm_cnt value is co mpared to the two buffers that are updated with the values of tm_data0 and tm_data1 register. when (tm_cnt + 1) is equal to the buffer of tm_data0, tm_mat_int0 interrupt occurs and the timer continues the counting operation
S5L840F 16 bits timer 13 without clearing the counter. when (tm_cnt + 1) is equal to the buffer of tm_data1, the timer generates tm_mat_int1 interrupt, clears thetm_cnt register, and updates the internal buffers with the values of tm_data0 register and tm_data1 register. for each interrupt, the tm_out is toggled. as the values of tm_data0 and tm_data1 register are updated after the tm_mat_int1 interrupt, the new values in tm_d ata0 and tm_data1 registers have an effect after tm_mat_int1 occurs. this mode is used to generate a configurable pwm signal. the clock period of pwm signal can be set in tm_data1 register and the duty ratio can be set in tm_data0 register. the operation of this mode is described in the figure 4. tm_cnt value tm_data1 =200 200 200 200 100 write tm_data0 = 100 start tm_data0=150 tm_data1=200 (period=200) write write tm_data0 = 50 tm_data1= 100 (period change) 150 75 50 100 0 tm_data1 =200 tm_data1 =200 tm_data1 =100 tm_data0 = 75 tm_out figure 4. pwm mode operation depending on the values of the tm_data0 and tm_data1, the shapes of the pwm signals are different. the detailed waveforms in pwm mode are shown in figure 6, figure 7, figure 8, and figure 9.
S5L840F 16 bits timer 14 pclk counting enable tm_cnt pwm mode, tm_data0 = 1, tm_data1 = 2, tm_start = 1 tm_out 0000 0001 0000 0001 tm_en tm_clr data0_buf data1_buf 0001 0002 intr (mat_int1) intr (mat_int0) initially tm_data0 = 1 and tm_data1 = 2 figure 6. pwm signal when tm_data0 = 1 and tm_data1 = 2 pclk counting enable tm_cnt pwm mode, tm_data0 = 0, tm_data1 = 0, tm_start = 1 tm_out 0000 0000 0000 0000 tm_en tm_clr data0_buf data1_buf 0000 0000 intr (mat_int1) intr (mat_int0) initially tm_data0 = 0 and tm_data1 = 0 figure 7. pwm signal when tm_data0 = 0 and tm_data1 = 0
S5L840F 16 bits timer 15 pclk counting enable tm_cnt pwm mode, tm_data0 = 0, tm_data1 = 2, tm_start = 1 intr (mat_int1) tm_out 0000 0001 0000 0001 tm_en tm_clr data0_buf data1_buf 0000 0002 intr (mat_int0) initially tm_data0 = 0 and tm_data1 = 2 figure 8. pwm signal when tm_data0 = 0 and tm_data1 = 2 (duty ratio = 0 %) pclk counting enable tm_cnt pwm mode, tm_data0 = 2, tm_data1 = 2, tm_start = 1 tm_out 0000 0001 0000 0001 tm_en tm_clr data0_buf data1_buf 0002 0002 intr (mat_int1) intr (mat_int0) initially tm_data0 = 2 and tm_data1 = 2 figure 9. pwm signal when tm_data0 = 2 and tm_data1 = 2 (duty ratio = 100 %) one-shot mode
S5L840F 16 bits timer 16 one-shot mode is same as the pwm mode except that only one pwm signal pulse is generated. after generating one pwm signal, the flag, tm_en, in tm_com register is cleared to disable the timer. the operation of the one-shot mode is described in figure 10. tmdata0 match tmdata1 match tmdata0 value tmdata1 value tmcnt value start 0 one-shot pulse width = tmdata1-tmdata0 clear figure 10. one-shot mode operation capture mode capture mode is used to capture the external signal from the tm_cap. when a timer is enabled in this mode, the internal counter continues the counting and the timer waits an event on the tm_cap port. when a falling or rising transition occurs on the tm_cap port, the value of the counter register is captured to the data regi sters (tm_data0 or tm_data1) and an interrupt is generated (tm_mat_int0 or tm_mat_int1). captur e mode has two distinct modes: rising edge clear mode and falling edge clear mode. the tm_c ap_mode flag in the tmcon register sets these modes. in rising edge clear mode by setting tm_cap_mode to 0, when a falling edge is detected, the count value is captured to the tm_data0 and an interrupt tm_mat_int0 is generated. on the other hand, when a rising edge on the tm_cap por t is detected, the count value is also captured to the tm_data1, an interrupt tm_mat_int1 is generated and the count register is cleared to zero. in this mode, the internal counter is cleared when an rising event is detected on the tm_cap port. the detailed description is shown in fig 8.
S5L840F 16 bits timer 17 tmcap tmcnt 0 150 clear interrupt falling edge rising edge tmmat_int0 tmmat_int1 tmmat_int0 tmmat_int1 400 tmdata0 200 450 50 tmdata1 150 200 50 xxx xxx 400 450 fig 8. capture mode in rising edge clear mode the falling edge clear mode is reverse to the rising edge clear mode. when a rising edge is detected on the tm_cap port, the count value is captured to tm_data0 and an interrupt, tm_mat_int0, is generated. when a falling edge occurs, the count value is stored to tm_data1, tm_mat_int1 occurs and the count register is cleared. by using the capture mode, you can get all the needed information of a pwm signal: duty ratio and the period. counting clock division the internal clock is counted by a clock which is prescaled by tm_pre register and clock selection. the clock selected by tm_cs is pre defined clocks or external clocks. the predefined clocks are derived from the main clock. there are two external clocks. they can be used for accurate sync with an external logic that is not synchronous with the main clock. the internal counter counts up with the rising edge of the external clock. the clock selected by the tm_cs is scaled by the tm_pre register. the frequency of the scaled clock is as follows: scaled clock [hz] = source clock [hz] / (tm_pre + 1) the source clock is the selected clock by the tm_cs. table 1 and table 2 shows the frequency and the period for each clock selection. it assumes that the main clock is 121.5 mhz.
S5L840F 16 bits timer 18 tm_pre = 0 tm_pre = 1024 count clock overflow (x65536) count clock overflow (x65536) tm_cs frequency/ period frequency/ period frequency/ period frequency/ period frequency/ period 1.90 mhz 1.90 mhz 28.97 hz 1.85 khz 0.03 hz main clock / 64 526.75 ns 526.75 ns 34.52 ms 539.39 ms 35.35 s 7.59 mhz 7.59 mhz 115.87 hz 7.42 khz 0.11 hz main clock / 16 131.69 ns 131.69 ns 8.63 ms 134.85 ms 8.84 s 30.38 mhz 30.38 mhz 463.49 hz 29.66 khz 0.45 hz main clock / 4 32.92 ns 32.92 ns 2.16 ms 33.71 ms 2.21 s 60.75 mhz 60.75 mhz 926.97 hz 59.33 khz 0.91 hz main clock / 2 16.46 ns 16.46 ns 1.08 ms 16.86 ms 1.10 s table 1. pre-scaled clock frequency and period when main clock = 121.5 mhz
S5L840F 16 bits timer 19
s3c49f8x multimedia card controller 1/13 ??? nand flash memory controller overview this module can control the interface of the external nand flash memory . features flash memory controller(fmc) su pports the following function. z supports 64/128/256/512mbit,1g, 2g,4gbit nand flash memory made by samsung. z can be connected up to 3 flash memory. z supports only one flash memory at a time. z ecc supported z for ecc, the parity bit encoding and decoding
s3c49f8x multimedia card controller 2/13 ??? block diagram fmc_dma fmc_out fmc_fsm fmc_rs_enc_16 fmc_ecc_misc fmc_rbb_insample fmc_reg_n_dbuf fmc_rs_dec fmc_rs_enc fmc_rs_dec_16 fmc_synd_outbuf_ctrl dnac k dnre q read y bus y pclk presetn penable pselfmc paddr pwrite pwdata prdata fmio out p u t fmio enb fmio in p u t ceb0 ceb1 ceb2 web reb w p b cle ale
s3c49f8x multimedia card controller 3/13 ??? pin description for flash memory diagram part port name description pclk presetn pselfmc paddr[5:0] pwrite pwdata[15:0] apb prdata[15:0] amba apb protocol fmio_enb flash io output enable, low active. fmio_input[15:0] flash io input fmio_output[15:0] flash io output ceb0 chip0 select ceb1 chip1 select ceb2 chip2 select web write enable reb read enable seb spare area enable ( deleted ) wpb wrote protect cle command latch enable flash ale address latch enable d_nack dma acknowledge dma d_nreq dma request
s3c49f8x multimedia card controller 4/13 ??? function description overview this fmc support 64mb, 128mb, 256mb, 512m b, 1gb, 2gb and 4gb nand flash memory which are made by samsung. user can do that fmc is enabled or disabled using control register in fmc. the ecc scheme used in this fmc is rs-code. the main features are : - nand flash controller - support 64mb/128mb/256mb/512mb/1g b/2gb/4gb nand flash components - support 8bit or 16bit interface. - embedded 1-symbol ecc (r s-code) encoder/decoder - there are two ways for data transfer, by cpu or dma. . flash memory controller operation description after reset is active, fmc will be disabled. all of registers are cleared in this state. fm c is enabled or disabled by control register. the operation sequence is the following : 1) read the id register for getting the inform ation of the connected external flash memory. from the content of id register, user can also get the version of fm. 2) set the density register and control register. the signal named by fmc_en in control regist er is the signal for fmc to be enabled or disabled. after this signal is toggled from lo w to high, the density register has to be set again. in case of ecc mode, after write operation, the syndrome data generated has to be saved for read operation. in case that r ead operation is executed in ecc mode, user has to write the syndrome data in syndrome register prior to reading. 3) user can get the status of the current operation by reading the status register.
s3c49f8x multimedia card controller 5/13 ??? flash memory controller register address r/w register name base address + 0x00 r/w command register fmcmd base address + 0x04 r/w column address register1 fmcaddr1 base address + 0x08 r/w column address register2 fmcaddr2 base address + 0x0c r/w row address register1 fmraddr1 base address + 0x10 r/w row address register2 fmraddr2 base address + 0x14 r/w row address register3 fmraddr3 base address + 0x18 r flash memory status register (cmd = 70h) fmrstatus base address + 0x1c r flash memory id register0 (cmd = 90h) fmrid0 base address + 0x20 r flash memory id register1 (cmd = 90h) fmrid1 base address + 0x24 r flash memory id register2 (cmd = 90h) fmrid2 base address + 0x28 r flash memory id register3 (cmd = 90h) fmrid3 base address + 0x2c r flash memory id register4 (cmd = 90h) fmrid4 base address + 0x30 r/w control register fmctrl base address + 0x34 r/w ecc decoder control register fmcdectrl base address + 0x38 r controller status register fmcstatus base address + 0x3c r ecc decoder status register fmcdecstatus base address + 0x40 r/w data register0 ~ 7 fmdatardwr0 ~ 7 base address + 0x60 r/w syndrome data0 gen erated at write operation fmsyndoutrw0 base address + 0x64 r/w syndrome data1 gen erated at write operation fmsyndoutrw1 base address + 0x68 r/w syndrome data2 gen erated at write operation fmsyndoutrw2 base address + 0x6c r/w syndrome data3 generated at write operation fmsyndoutrw3 base address + 0x80 r/w syndrome data0 used for read operation fmsyndinrw0 base address + 0x84 r/w syndrome data1 used for read operation fmsyndinrw1 base address + 0x88 r/w syndrome data2 used for read operation fmsyndinrw2 base address + 0x8c r/w syndrome data3 used for read operation fmsyndinrw3 base address + 0x90 r/w syndrome data0 used for read operation fmdec_result0 base address + 0x94 r/w syndrome data1 used for read operation fmdec_result1 base address + 0x98 r/w syndrome data2 used for read operation fmdec_result2 base address + 0x9c r/w syndrome data3 used for read operation fmdec_result3 base address + 0xa0 r/w density of flash that will be used fmdensity base address + 0xa4 r/w fsm of controller fmtest
s3c49f8x multimedia card controller 6/13 ??? flash memory controller register descriptions fmcmd initial value is 0x00. the command will be sent to fm is written in this register. bit[15:8] bit[7:0] not used command address_n register (fmcaddrn/fmraddrn) initial valures are 0x00. there are 5 address regi sters. the column address is written in fmcaddrn and the row address is written in fmraddrn as to the density type of external flash memory. (ex : 512mb read : fmcaddr1 ? fmraddr1 ? fmraddr2 ? fmraddr3 512mb erase : fmraddr1 ? fmraddr2 ? fmraddr3 ) bit[15:8] bit[7:0] not used address external flash memory status register (fmrstatus) initial value is 0x00. after writing 0x70 command(read status) to fm, fm outputs the contents of fm status. those content are written in fmrstatus regist er. user can find out whether program or erase operation is completed, and whether t he program or erase operation is completed successfully. bit[15:8] bit[7:0] not used status of flash
s3c49f8x multimedia card controller 7/13 ??? external flash memory idn register (fmridn) initial value is 0x00. after writing 0x90 command (read id) and an address input, fm(flash memory) send the product identification. those informatio n is written in fmridn register. bit[15:8] bit[7:0] not used flash id control register (fmctrl) bit operation function 0 (ceb1 enable) 0 = disable 1 = enable the ceb1 is enabled when need to flash1. the inverse value of this bit outputs to external flash memoy/ 1 (fmc_en) 0 = disable 1 = enable user can initiate all of registers in fmc. 2 reserved 3 (random_cben) 0 = disable 1 = enable select whether to use the copy-back with random data input function 4.(copybacken) 0 = disable 1 = enable select whether to use the copy-back function 5 (ecc_en) 0 = disable 1 = enable select whether to use the ecc function 6 reserved 7 (nwp) 0 = enable 1 = disable nwp must be high in write mode and don?t care in read mode 8 (ceb2 enable) 0 = disable 1 = enable the ceb2 is enabled when need to flash2. the inverse value of this bit outputs to external flash memoy/ 9(ceb0 enable) 0 = disable 1 = enable the ceb0 is enabled when need to flash0. the inverse value of this bit outputs to external flash memoy/ 10 (little endian) 0 = little endian 1 = big endian select whether the data transfer type is little endian or big endian. 11(version _inf) 0 = single die flash 1 = double die flash select whether the memoy type is single die or double die. 14:12 (sig_wait) ex) pclk 100mhz = 4 (sig_wait) 50mhz = 2 (sig_wait) 30mhz = 0 (sig_wait) flash control signal hold the current level for (sig_wait +1) pclk 15 (data_width) 0 : flash io = x8 1: flash io = x16 select whether the data bit width transferred is 8bit or 16bit.
s3c49f8x multimedia card controller 8/13 ??? ecc control register (fmcdectrl) the initial value is 0x0000. after ecc function is enabled, the 4bit named dec_synd_flagn have to be enabled to do read operation with ecc before the contents of syndrome input buffer is changed. the description of each bit is as following: bit operation function 0 (dec_synd_flag0) 1 (dec_synd_flag0) 2 (dec_synd_flag0) 3 (dec_synd_flag0) 0 = disable ecc decoder when read operation 1 = enable ecc decoder when read operation select whether to use the ecc decoder. each bit is used for being enable the syndrome data , bit0 is used for 1 st 128byte data, bit1 is used for 2 nd 128byte data, bit3 is used for 3 rd 128 byte data bit4 is used for 4 th 128byte data 4 rd_end read stop while the read operation is executed with ecc, if this bit is high, read operation will be stopped after decode is finished. 5 (clr_inbuf_wr_ptr) 0 = don?t care 1 = clear the pointer to 3?b000 when user don?t read data by 512byte, this bit must be used before read operation 6 dmaen 0 = disable 1 = enable 7 reserved 8 reserved 15:8 not used
s3c49f8x multimedia card controller 9/13 ??? fmc status register (fmcstatus) the initial value is 0x00. user has to check this register while the flow of each program. bit operation function 0 (readybusyb) 0 = busy 1 = ready the status of current operation in fm is busy or ready. 1 reserved 2 (rdid_end_flag) 1 = flash id read end after flash id command, all flash id bytes are read from flash 3 reserved 4 reserved 5 (status_data_set) 0 = not ready 1= ready when the status data transfers to fmrstatus by 70h command, this bit is set. after cpu read fmrstatus, this bit will be cleared 6 (last_column) 0 = not last column 1 = last column when ?1? is setting, it indicates the last column at that page. 7 (add_send_end) 1 = address-send-end indicate that all address bytes are send to flash as to command. 8(outbuf_rdend) 1=output buffer empty indica tes data buffer(fifo) are empty during write operation, cpu should write 8 data(width 16) if this bit is high 9(inbuf0_ready) 1=input buffer full indicates the first fifo are full when read operation. cpu can read 8 data 10(inbuf1_ready) 1=input buffer full indicates the second fifo are full when read operation. cpu can read 8 data 11 reserved 12 reserved 15:13(column_cnt) column_cnt[2:0] while read or write operation is doing, this counter indicate the data number transferred.
s3c49f8x multimedia card controller 10/13 ??? ecc status register (fmcdecstatus) the initial value is 0x0000.. bit function 0 (dec_no_error0) 1 (dec_no_error0) 2 (dec_no_error0) 3 (dec_no_error0) 0 = error 1 = no error each bit is used for indicating whether to occur the ecc decoding error. the bit0 indicates the occurrence of the error for 1 st 128byte data, bit1 for 2 nd 128byte data, bit3 for 3 rd 128 byte data and bit4 for 4 th 128byte data 4 (dec_end0) 5 (dec_end0) 6 (dec_end0) 7 (dec_end0) 0 = progressing 1 = decoding end each bit is used for indicating whether to end ecc decoding operation, bit4 for 1 st 128byte data, bit5 for 2 nd 128byte data, bit6 for 3 rd 128 byte data and bit7 for 4 th 128byte data 15:8 not used data register (fmdatardwrn) the initial value is 0x00. the width is 16bit. there are 8 registers. these registers are used to store data transmitted or received. cpu have to write the data when the bit[8] of thisregisteris high in write mode. in read mode, cpu have to read the data from th is register after checking that the bit[9] or bit[10] is high. at first, user check the bit[10[ after checking bit[9]. then check those bits in turn. x16, x8 512byte fmcdatardwr0 ~7
s3c49f8x multimedia card controller 11/13 ??? syndrome data output register (fmsyndoutrwn) the initial value is 0x00. there are 4 registers whose width is 16bit. the syndrome data generated from ecc encoder in write mode enter to thess registers. fmcsyndoutrw0 1 st 128byte data syndrome data(2byte) fmcsyndoutrw1 2 nd 128byte data syndrome data fmcsyndoutrw2 3 rd 128byte data syndrome data fmcsyndoutrw3 4 th 128byte data syndrome data to transfer these value to external fm, at first, cpu read these register. after that, cpu write thes e data to fmdatardwrn. the way of transfer is same to normal syndrome data input register (fmsyndinrwn) the initial value is 0x00. there are 4 register whose width is 16bit. before read operation in ecc mode, cpu have to write the syndrome data to these register in just order. if the read operation is finished after writing syndrome data, user can the occurrence of error by chec king dec_status register. fmcsyndinrw0 1 st 128byte data syndrome data(2byte) fmcsyndinrw1 2 nd 128byte data syndrome data fmcsyndinrw2 3 rd 128byte data syndrome data fmcsyndinrw3 4 th 128byte data syndrome data ecc decoding result register (fmdec_result) the initial value is 0xffff. there are 4 register whose width is 16bit. fmdec_result0 the result of 1 st 128byte data decoding(2byte) fmdec_result1 the result of 2 nd 128byte data decoding fmdec_result2 the result of 3 rd 128byte data decoding fmdec_result3 the result of 4 th 128byte data decoding
s3c49f8x multimedia card controller 12/13 ??? flash density register (fmdensity) after reading flash id, cpu have to set the density register. bit function 0 below 256m bit 1 512m bit 2 1g bit 3 2g bit 4 4g bit 15:5 not used flash controller fmc (fmtest) the state of fsm in fmc is written in this register.. bit function 4:0 fsm 15:5 ?0? * the flash type and command supported. ( vcc=2.7 ~ 3.6v, organization = x8, x16) command sets density (bits) function 1?st cycle 2?nd cycle 3?rd cycle id 64m read1 read2 read id reset page program block erase status read 00h/01h 50h 90h ffh 80h 60h 70h 10h d0h e6h 128m read1 read2 read id reset page program block erase status read 00h/01h 50h 90h ffh 80h 60h 70h 10h d0h 73h 256m read1 read2 read id reset page program block erase status read copy-back 00h/01h 50h 90h ffh 80h 60h 70h 00h 10h d0h 8ah 75h
s3c49f8x multimedia card controller 13/13 ??? 512m (single chip) read1 read2 read id reset page program block erase status read copy-back 00h/01h 50h 90h ffh 80h 60h 70h 00h 10h d0h 8ah 10h 76h 512m (double chip) read1 read2 read id reset page program block erase status read copy-back 00h/01h 50h 90h ffh 80h 60h 70h 00h 10h d0h 8ah 76h 1g (single chip) read read for copy-back read id reset page program cache program copy-back program block erase random input random output read status 00h 00h 90h ffh 80h 80h 85h 60h 85h 05h 70h 30h 35h 10h 15h 10h d0h e0h f1h 1g (double chip) read1 read2 read id reset page program block erase status read copy-back 00h/01h 50h 90h ffh 80h 60h 70h 00h 10h d0h 8ah 10h 79h 2g (single,double chip) read read for copy-back read id reset page program cache program copy-back program block erase random input random output read status 00h 00h 90h ffh 80h 80h 85h 60h 85h 05h 70h 30h 35h 10h 15h 10h d0h e0h dah 4g (double chip) read read for copy-back read id reset page program cache program copy-back program block erase random input random output read status 00h 00h 90h ffh 80h 80h 85h 60h 85h 05h 70h 30h 35h 10h 15h 10h d0h e0h dch
1 secure digital card interface (sdci) overview the secure digital card interface (sdci) can interface for sd m emory card and multi- media card(mmc). features y supports multimediacard sp ecification version 3.1 y supports sd memory card sp ecification version 1.0 y cards clock rate up to system clock(pclk) divided by 2 y 16 words (64 bytes) fifo (depth 16) for data transmit y 8 words (32 bytes) fifo (depth 8) for data receive y crc7 & crc16 generator/checker y normal, and dma data transfer mode y support for block and multi-b lock data read and write y 1bit/4bit(wide bus) mode switch support y can be directly connected to the amba peripheral bus (apb) vers ion 2.0
2 block diagram pclk presetn pselsdci penable pwrite paddr[7:2] pwdata[31:0] prdata[31:0] d_nreq d_nack apb i/f cmd control clock control dma control shift register crc7 dat control shift register crc16 tx fifo rx fifo command_output response_input clock_output dat_output[3:0] dat_input[3:0]
3 pin description pin name width i/o description system signals pclk 1 i clock presetn 1 i reset apb signals pselsdci 1 i selection on apb penable 1 i enable in apb pwrite 1 i write/read in apb paddr 6 i address in apb pwaddr 32 i write data in apb praddr 32 o read data in apb external signal wp_dect_input 1 i writ e protect pin input response_input 1 i response input(cmd) dat0_input 1 i data0 input(dat0) dat1_input 1 i data1 input(dat1) dat2_input 1 i data2 input(dat2) dat3_input 1 i data3 input(dat3) clk_output 1 o cloc k output(sdclk) command_output 1 o command output(cmd) command_enable 1 o command output enable dat0_output 1 o data0 output(dat0) dat0_enable 1 o data0 output enable dat1_output 1 o data1 output(dat1) dat1_enable 1 o data1 output enable dat2_output 1 o data2 output(dat2) dat2_enable 1 o data2 output enable dat3_output 1 o data3 output(dat3) dat3_enable 1 o data3 output enable dma relative signal d_nack 1 i dma request signal d_nreq 1 o dma acknowledge signal
4 sdci operation a serial clock line is synchronized with the command and 4 data lines for shifting and sampling of the information. making the appropriate bit settings to the sdc i_ctrl register depends on the transmission frequency. sdci configuration 1. after a hardware reset, by default, the sdci pins are deselecte d and the user must configure the gpio controller to assign pios to sdci peripheral functions . for details, refer to the gpio datasheet. cmd path programming -operation of broadcast commands (bc, bcr) and addressed comman ds (ac) 1. write the argument value to sdci_arg register. 2. write the command information to sdci_cmd register. - confirm the ready of command transmission when the specific fla g of sdci_sta[0]. 3. write the command start bit to sdci_cmd register. 4. check the status of sdci command operation. - command transmission is in progress, the sdci_sta[1] is set. - command transmission is completed, the sdci_sta[2] is set. - response reception is in progress, the sdci_sta[3] is set. - response reception is completed, the sdci_sta[4] is set. 5. check the status of response - if command response time-out error occur, the sdci_sta[16] is s et. - if response end bit error occur, the sdci_sta[17] is set. - if response index error occur, the sdci_sta[18] is set. - if response crc error occur, the sdci_sta[19] is set. 6. check the card response, read from sdci_resp3~0 register. 7. clear the corresponding flag of the sdci_sta register by write the sdci_stac register. dat path programming (not use dma) -operation of addressed data transfer commands (adtc) 1. write the data block length to the sdci_dctrl register. 2. fifo reset by writing the sdci_dctrl register. 3. do cmd path programming 4. write the data transmission start bit to sdci_dctrl[5:4] regist er(only data write operation).
5 5. when write operation, write tx data to sdci_txrx register while txfifo is available by checking sdci_sta[13:12]. 6. when read operation, read rx data to sdci_txrx register while r xfifo is available by checking sdci_sta[11:10]. 7. check the status of sdci data operation. - data transmission/reception is in progress, the sdci_sta[5] is set. - data block transmission/reception is completed, the sdci_sta[6] is set - data crc data transmission/reception is completed, the sdci_sta [7] is set. - crc status token reception is completed, the sdci_sta[8] is set , only write command. - card busy state, the sdci_sta[9] is set. 8. check the status of data transfer - if write data crc status token has error, set the sdci_sta[23] is set, crc status token value is set sdci_sta[22:10]. - if read data crc error occur, set the sdci_sta[24] is set. - if read data end bit error occur, set the sdci_sta[28:25] are s et. 9. clear the corresponding flag of the sdci_sta register by write the sdci_stac register. 10. if multiple data block transfer, repeat 4~9. dat path programming (using dma) 1. configure sdci as dma mode, control register set in dma module. 2. write the data block length to the sdci_dctrl register. 3. fifo reset by writing the sdci_dctrl register. 4. do cmd path programming 5. write the data transmission start bit to sdci_dctrl[5:4] regist er(only data write operation). 6. the sdci requests dma service. 7. dma transmits data to the sdci as dma configuration. 8. check the status of data transfer. 9. if multiple data block transfer, repeat 1, 5~8. note 1. in case of 136bit response, the crc error should be detected after receiving exact response data form sdcard or mmc. user should check the crc of receive respon se by software. 2. user should check the read, write and erase time-out error.
6 sdci register offset register name width read/write register name initial value 0x00 sdci_ctrl 32bit read/write control register 0x0000_0000 0x04 sdci_dctrl 32bit read/write data control register 0x0200_00 00 0x08 sdci_cmd 32bit read/write command register 0x0000_0000 0x0c sdci_arg 32bit read/write argument register 0x0000_0000 0x10 reserved 0x14 sdci_stac 32bit write status clear register 0x0000_0000 0x18 sdci_sta 32bit read status register 0x8000_1400 0x1c reserved 0x20 sdci_resp0 32bit read response0 register 0x0000_0000 0x24 sdci_resp1 32bit read response1 register 0x0000_0000 0x28 sdci_resp2 32bit read response2 register 0x0000_0000 0x2c sdci_resp3 32bit read response3 register 0x0000_0000 0x30 sdci_txrx 32bit read/write data register 0x0000_0000 sdci control (sdci_ctrl) register bit name description 31:16 reserved 15:8 clkdiv select the sdclk 0000_0001 0000_0010 0000_0100 0000_1000 0001_0000 0010_0000 0100_0000 1000_0000 else sdclk = pclk/2 sdclk = pclk/4 sdclk = pclk/8 sdclk = pclk/16 sdclk = pclk/32 sdclk = pclk/64 sdclk = pclk/128 sdclk = pclk/256 reserved 7:6 reserved 5 dma_req_con select dma request condition, only read command 0 1 dma request when receive fifo is not empty. dma request when receive fifo is full. 4 l_endian select endian
7 0 1 big endian little endian 3 dmaen dma enable 0 1 dma disable dma enable 2 bus_width select the sdcard bus width. only use sdcard (card_type == 1b0) 0 1 1bit data bus 4bit data bus 1 card_type select the card type 0 1 sd card mm card 0 sdcien sdci block enable 0 1 disable the sdci enable then sdci sdci data control (sdci_dctrl) register bit name description 31:16 blk_len determine the data block size (unit : byte) 15:6 reserved 5:4 trcont start the data transfer, automatically cleared. only write command (cmd_class ==2b11). 00 01 1x no effect data transmission start reserved 3:2 reserved 1 rxfiforst reset the receive fifo. 0 1 no effect reset the receive fifo 0 txfifirst reset the transmit fifo. 0 1 no effect reset the transmit fifo sdci command (sdci_cmd) register bit name description
8 31 cmdstr start the command transfer, automatically cleared. only writable when sdci_sr[0] = 1. 0 1 no effect command transmit start 30:21 reserved 20 ncr_nid select the clock cycle command to response. 0 1 n cr (64 clock cycle) n id (5 clock cycle) 19 res_size select the response size 0 1 48 bit size response 136 bit size response 18:16 res_class select response class 000 001 010 011 100 101 110 111 no response r1, r1b r2 r3 r4 r5 r6 reserved 15:9 reserved 8 cmd_type select the command type 0 1 general command application command 7:6 cmd_class select the command class 00 01 10 11 broadcast commands addressed commands addressed data transfer commands - read command addressed data transfer commands C write command caution : use cmd13 during read/write operation, cmd_class value must maintain the existing value. 5:0 cmd_num set the command number sdci argument (sdci_arg) register bit name description
9 31:0 argument set the argument value sdci status clear (sdci_stac) register bit name description 31:29 reserved 28 clr_rd_datende3 clear rd_datende3 at sdci_sr 0 1 no effect clear the rd_datemde3 bit 27 clr_rd_datende2 clear rd_datende2 at sdci_sr 0 1 no effect clear the rd_datemde2 bit 26 clr_rd_datende1 clear rd_datende1 at sdci_sr 0 1 no effect clear the rd_datemde1 bit 25 clr_rd_datende0 clear rd_datende0 at sdci_sr 0 1 no effect clear the rd_datemde0 bit 24 clr_rd_datcrce clear rd_datcrce at sdci_sr 0 1 no effect clear the rd_datcrce bit 23 clr_wr_datcrce clear wr_datcrce at sdci_sr 0 1 no effect clear the wr_datcrce bit 22:20 reserved 19 clr_rescrce clear rescrce at sdci_sr 0 1 no effect clear the rescrce bit 18 clr_resinde clear resinde at sdci_sr 0 1 no effect clear the resinde bit 17 clr_resende clear resende at sdci_sr 0 1 no effect clear the resende bit 16 clr_restoute clear restoute at sdcr_sr 0 no effect
10 1 clear the restoute bit 15:9 reserved 8 clr_crc_staend clear crc_staend at sdci_sr 0 1 no effect clear the crc_staend bit 7 clr_dat_crcend clear dat_crcend at sdci_sr 0 1 no effect clear the dat_crcend bit 6 clr_datend clear dat_end at sdci_sr 0 1 no effect clear the datend bit 5 reserved 4 clr_resend clear resend at sdci_sr 0 1 no effect clear the resend bit 3 reserved 2 clr_cmdend clear cmdend at sdci_sr 0 1 no effect clear the cmdend bit 1:0 reserved sdci status (sdci_sta) register clear condition: a : according to the sdci interface state. c : clear by write 1 to corresponding bit of sdci_scr. bit name description clear condition 31 wp_dect_input wp pin status 0 1 wp pin status is low wp pin status is high a 30:29 reserved 28 rd_datende3 read data end bit error on dat3 0 1 no read data end bit error of dat3 occurs read data end bit error of dat3 occurs c
11 27 rd_datende2 read data end bit error on dat2 0 1 no read data end bit error of dat2 occurs read data end bit error of dat2 occurs c 26 rd_datende1 read data end bit error on dat1 0 1 no read data end bit error of dat1 occurs read data end bit error of dat1 occurs c 25 rd_datende0 read data end bit error on dat0 0 1 no read data end bit error of dat0 occurs read data end bit error of dat0 occurs c 24 rd_datcrce read data has crc error 0 1 no read data crc error occurs read data crc error occurs c 23 wr_datcrce write data crc status response has error 0 1 no crc status token error occurs crc status token error occurs c 22:20 wr_crc_status write data crc status response value 010 101 111 else non erroneous transmission transmission error card error reserved a 19 rescrce response crc error. not valid, when res_class = 3001. 0 1 no response crc error occurs response crc error occurs c 18 resinde response index error 0 1 no response index error occurs response index error occurs c 17 resende response end bit error 0 1 no response end bit error occurs response end bit error occurs c 16 restoute response timeout error (ncr, nid) 0 1 no command to response timeout error occurs command to response timeout error occurs c 15:14 reserved
12 13 tx_fifo_full tx fifo full 0 1 transmit fifo is not full transmit fifo is full a 12 tx_fifo_empty tx fifo empty 0 1 transmit fifo is not empty transmit fifo is empty a 11 rx_fifo_full rx fifo full 0 1 receive fifo is not full receive fifo is full a 10 rx_fifo_empty rx fifo empty 0 1 receive fifo is not empty receive fifo is empty a 9 dat_busy data line busy 0 1 card is not busy card is busy this status is direct connected inverted dat0 of card. a 8 crc_staend write data crc status token receive end 0 1 crc status token reception is not ended crc status token reception is ended c 7 dat_crcend data crc transmit/receive end 0 1 crc transmission/reception is not ended crc transmission/reception is ended c 6 datend data transmit/receive end 0 1 data transmission/reception is not ended data transmission/reception is ended c 5 datpro data transfer in progress 0 1 data transmission/reception is not in progress data transmission/reception is in progress a 4 resend response receive end 0 1 response reception is not ended response reception is ended c 3 respro response receive in progress 0 response reception is not in progress a
13 1 response reception is in progress 2 cmdend command transfer end 0 1 command transmission is not ended command transmission is ended c 1 cmdpro command transfer in progress 0 1 command transmission is not in progress command transmission is in progress a 0 cmdrdy command ready 0 1 command transfer is not ready command transfer is ready (sdci_cmd, sdci_arg set complete) a sdci response3 (sdci_resp3) register bit name description 31:0 response3 the res_size determines the value res_size response3 0 1 32h0000_0000 response[127:96] sdci response2 (sdci_resp2) register bit name description 31:0 response2 the res_size determines the value res_size response2 0 1 32h0000_0000 response[95:64] sdci response1 (sdci_resp1) register bit name description 31:0 response1 the res_size determines the value res_size response1 0 1 32h0000_0000 response[63:32]
14 sdci response0 (sdci_resp0) register bit name description 31:0 response0 the res_size determines the value res_size response0 0 1 response[39:8] response[31:0] sdci data (sdci_txrx) register bit name description 31:0 sdci_txrx data buffer for transmit/receive note: if data is not aligned to word(4byte), sdci_txrx register value is following table(big_endian). when data read write data sdci_txrx[31:24] sdci_txrx[13:16] sdci_txrx[15:8] sdc i_txrx[7:0] 4n+1 byte write data[7:0] stuf f bits stuff bits stuff bits 4n+2 byte write data[7:0] write data[15:8] stuff bits stuff bit s 4n+3 byte write data[7:0] write data[15:8] write data[23:16] st uff bits when data write read data sdci_txrx[31:24] sdci_txrx[13:16] sdci_txrx[15:8] sdci _txrx[7:0] 4n+1 byte 0x00 0x00 0x00 read data[7:0] 4n+2 byte 0x00 0x00 read data[7:0] read data[15:8] 4n+3 byte 0x00 read data[7:0] read data[15:8] read data[23:16]
S5L840F memory stick host controller 15-1 15 memory stick host controller overview ? protocol is started by writing to the command register from the cpu ? data is requested by dma or interrupt to the cpu when entering the data period ? rdy timeout period can be set by the number of serial clock ? interrupt can also be output to the cpu when a timeout occurs ? crc can be turned off during test mode ? built-in 4-bit parallel port ? 16-bit access ? the output from fifo is little endian feature ? built-in 8-byte (4-word) fifo buffers for transmit and receive respectively ? built-in crc circuit ? transfer clock up to 80 mhz (exnternal inpu t. when using the sony c5mx-hb-t library.) ? dma supported ? automatic command execution (can be turned on/off) when an int from the memory stick is detected ? magicgate supported ? approx. 8k gates (when using the sony c5mx-hb-t library) ? all registers are described pos itive edge flip flop (for scan)
memory stick host controller S5L840F 15-2 block diagram apb interface prescaler memory stick core sclki bs dack sclko sdir sdio_out po[3:0] sdio_in pi[3:0] apb interface i/o dma interface dreq memory stick interface figure 15-1. memory stick host controller block diagram registers prescaler control register(mspre) register address r/w description reset value mspre 3c600000h r/w prescaler register 32 bits mspre bit description initial state clk_en [8] sclk (xsclk) output or not 0 = disable the sclk (xsclk) output 1 = enable the sclk (xsclk) output 0h prescale [7:0] prescale register to generate the sclk (xsclk) from the main clock. sclk [hz] = {main clock [hz] / (ms_pre + 1)} / 2 0h
S5L840F memory stick host controller 15-3 interrupt enable register(msinten) register address r/w description reset value msinten 3c600004h r/w interrupt enable register 32 bits msinten bit description initial state core_int_stat [12] interrupt generated by the memory st ick host controller. writing one clears this flag. user should write one to this field and read the msint register to deactivate the interrupt signal from the memory stick host controller. the sequence is not important. 0h rbe_int_stat [11] rbe interrupt status. writing one clears this flag and deactivates the interrupt. 1h rbf_int_stat [10] rbf interrupt status. writing one clears this flag and deactivates the interrupt. 0h tbe_int_stat [9] tbe interrupt status. writing one clears this flag and deactivates the interrupt. 1h tbf_int_stat [8] tbf interrupt status. writing one clears this flag and deactivates the interrupt. 0h rbe_int_en [3] interrupt enable/disable for the rbe. 0 = disable the interrupt from rbe 1 = enable the interrupt from rbe 0h rbf_int_en [2] interrupt enable/disable for the rbf. 0 = disable the interrupt from rbf 1 = enable the interrupt from rbf 0h tbe_int_en [1] interrupt enable/disable for the tbe. 0 = disable the interrupt from tbe 1 = enable the interrupt from tbe 0h tbf_int_en [0] interrupt enable/disable for the tbf. 0 = disable the interrupt from tbf 1 = enable the interrupt from tbf 0h
memory stick host controller S5L840F 15-4 command register(mscmd) register address r/w description reset value mscmd 3c601000h r/w command register 32 bits adcpara bit description initial state pid [15:12] packet id writing to command register starts the protocol. crc16bit is transfered during the data period even if the data size is 0. pid command is disabled if the data size is 0 and the nocrc bit of the control register 1 is 1. data cannot be written to the command register when the rdy bit of the interrupt control and data register is 0. (while the protocol is executing.) 0h data_size [9:0] data size for each trans fer. the pid determines the value. 0h
S5L840F memory stick host controller 15-5 control/status register(msctrlstat) register address r/w description reset value msctrlstat 3c601004h r/w control/status register 32 bits msctrlstat bit description initial state rst [15] internal reset 0 = nothing 1 = internal reset 0h reserved [14] reserved to 0 0h sien [13] serial interface enable 0 = disable the serial interface 1 = enable the serial interface 0h reserved [12] reserved to 0. 0h nocrc [11] data is transmitted/receiv ed without adding a crc (16bit) at the end of the data. normally this bit is set to zero during the operation. 0 = enable the crc 1 = disable the crc 0h bsycnt [10:8] rdy timeout time setting (serial clock count). this field is set to the maximum bsy timeout time (bsycnt x 4 + 2) to wait until the rdy signal is output from the memory stick. rdy timeout error detection is not performed when bsycnt = 0. initial value is 05h (22 sclk). 05h int [7] indicates the interrupt status 0 = when an interrupt condition is not generated 1 = when an interrupt condition is generated 0h drq [6] indicates dma request status 0 = when data is not requested 1 = when data is requested 0h rbe [3] receive buffer empty. 0 = the receive data buffer is not empty 1 = the receive data buffer is empty 1h rbf [2] receive buffer full. 0 = the receive data buffer is not full 1 = the receive data buffer is full 0h tbe [1] transmit buffer empty. 0 = the transmit data buffer is not empty 1 = the transmit data buffer is empty 1h tbf [0] transmit buffer full. 0 = the transmit data buffer is not full 1 = the transmit data buffer is full 0h
memory stick host controller S5L840F 15-6 operation performed during reset operations when rst is "1". a value of "1" should be maintained for the rst bi t for system clock 2 clocks and sclki 2 clocks and then must be returned to "0" in order to perform re set in sync with the clock. if the software-reset operation is executed, the following condition is set. register operation (status after rst = 1 and immediately after rst = 0) mscmd register = 0x00000000 msctrlstat register = 0x0000050a msfifo register = 0x00000000 msint register = 0x00000080 mspp register = 0x00000000 msctrl2 register = 0x00000000 msacd register = 0x00007001 output signal bs (bus state) = low level sdio_out (sdio output) = low level sclko (memory stick clock) = low level int = low level ndrq (dma request) = high level internal operation ? the transmit/receive data buffers are cleared ? tbe, rbe = 1 ? tbf, rbf = 0 ? po = 0 the executing protocol is terminated. receive/transmit dat a buffer(msfifo) register address r/w description reset value msfifo 3c601008h r/w receie/transmit register 32 bits msfifo bit description initial state rdata_buf [15:0] data buffer for receive ? when rbe is one, invalid data is read. 0h tdata_buf [15:0] data buffer for transmit ? when tbf is one, invalid data is ignored. 0h
S5L840F memory stick host controller 15-7 interrupt control/data register(msint) register address r/w description reset value msint 3c60100ch r/w interrupt control/data register 32 bits msint bit description initial state inten [15] xint interrupt enable 0 = xint interrupt signal output is disabled. 1 = xint interrupt signal output is enabled. 0h drqsl [14] 0 = xint output is disabled during data transfer request. 1 = xint output is enabled during data transfer request. 0h pinen [13] 0 = xint output is disabl ed by the change of the value in the xpi[3:0]. 1 = xint output is enabled by the change of the value in xpi[3:0]. 0h rdy [7] protocol status 0 = protocol with the memory stick is not ended. 1 = protocol with the memory stick is ended. this flag is cleared to zero when writing to the command register. 1h sif [6] serial interface interrupt 0 = serial i/f does not receive an interrupt 1 = serial i/f receives an interrupt. an interrupt signal is output separately from rdy interrupt. 0h drq [5] dma request 0 = xdrq (dma request) is not requested. 1 = when xdrq (dma request) output is requested and drqsl bit is 1. 0h pin [4] parallel port input change 0 = parallel inputs are not changed. 1 = when parallel inputs are changed and pinen is 1. 0h crc [1] crc error 0 = no crc error occurs. 1 = crc error occurs. cleared to zero when data is written to command register (mscmd). bs output is set to zero, rdy becomes to one, and an interrupt signal is generated. 0h toe [0] time out error 0 = no time out error occurs 1 = bsy timeout error occurs cleared to zero when data is written to the command register (mscmd) rdy becomes to one and an interrupt signal is output 0h
memory stick host controller S5L840F 15-8 parallel port control/data register(mspp) register address r/w description reset value mspp 3c601010h r/w parallel port control/data register 32 bits mspp bit description initial state pien [15:12] parallel port input enable 0 = parallel port inputs are disabled 1 = parallel port inputs are enabled 0h poen [11:8] parallel port output enable 0 = parallel port outputs are disabled 1 = parallel port outputs are enabled 0h xpin [7:4] parallel port input data ? xpin[n] is 1 when the pin pin is low level and 0 when high level. ? it takes 32 sclk cycles for a value from the parallel input pin pi[3:0] to be reflected at the xpin[3:0] 0h pout [3:0] parallel port output data ? high level is output when the pout[n] is set to 1 ? low level is output when the pout[n] is set to 0 0h control register 2(msctrl2) register address r/w description reset value msctrl2 3c601014h r/w control register 2 32 bits msctrl2 bit description initial state acd [15] auto command enable 0 = disable the auto command 1 = enable the auto command afte r an interrupt is detected. this flag is automatically cleared to zero after auto command processing is ended. 0h red [14] edge selection for data loading 0 = serial data is loaded at the rising edge of the clock 1 = serial data is loaded at the falling edge of the clock 0h auto command is a function used to automatically exec ute the get_int or read_r eg on the host interface. with this function, the interrupt signal from the me mory stick is detected and the command set in the acd command register is executed. when crc error or toe occurs, the auto command processing is terminated without performing acd and an in terrupt signal is generated.
S5L840F memory stick host controller 15-9 acd command register(msacd) register address r/w description reset value msacd 3c601018h r/w acd command register 32 bits msacd bit description initial state apid [15:12] pid code (transport protocol command) 7h adata_size [9:0] data size for each tr ansfer. the pid determines the value. 1h auto command is a function used to automatically exec ute the get_int or read_r eg on the host interface. with this function, the interrupt signal from the me mory stick is detected and the command set in the acd command register is executed.
memory stick host controller S5L840F 15-10 notes
S5L840F usb device 19-1 16 usb device controller overview universal serial bus (usb) device controller is des igned to provide a high performance full speed function controller solution with dma interface. usb device controlle r allows bilk transfer with dma, interrupt transfer and control transfer usb device controller support : - full speed usb device controller compatible with the usb specification version 1.1 - dma interface for bulk transfer - four endpoint with fifo ep0 : 16 bytes (register) ep1 : 64 bytes in/out fifo ep2 : 64 x 2 bytes in/out fifo ep3 : 64 x 2 bytes in/out fifo - integrated usb transceiver feature ? fully compliant with usb specification version 1.1 ? full speed (12mbps) device ? integrated usb transceiver ? supports control, interrup t, isochronous and bulk transfer ? four endpoints with fifo ? supports dma interface for receive and transmit bulk endpoint. (ep1, ep2 and ep3) ? support suspend and remote wakeup function.
usb device S5L840F 16-2 block diagram sie siu gfi apb and dma interface usb transce i ver fifo apb in te rfa ce req[2:0] ack [2:0] dp dm figure -1. usb device controller block diagram usb device controller special registers this section describes detailed functionalities about register sets of usb device controller. all special function register is byte-accessible. common indexed registers depend on index r egister(index_reg) value. for exam ple if you want to write ep0 csr register, you must write ?0x00? on the index_reg before writing in_csr1 register.
S5L840F usb device 16-3 register address description non indexed register func_addr_reg 3d100000h function address register pwr_mngnt_reg 3d100010h power management register ep_int_reg 3d100020h endpoint interrupt register usb_int_reg 3d100060h usb interrupt register ep_int_en_reg 3d100070h endpoint interrupt enable register usb_int_en_reg 3d1000b0h usb interrupt enable register frame_num1_reg 3d1000c0h frame number 1 register frame_num2_reg 3d1000d0h frame number 2 register index_reg 3d1000e0h index register dma_en_reg 3d1000f0h dma enable register ep0_fifo_reg 3d100200h endpoint0 fifo register ep1_fifo_reg 3d100210h endpoint1 fifo register ep2_fifo_reg 3d100220h endpoint2 fifo register ep3_fifo_reg 3d100230h endpoint3 fifo register common indexed registers maxp_reg 3d100130h endpoint max packet register in indexed registers in_csr1_reg/ep0_csr 3d100110h ep in control status register1/ ep0 control status register in_csr2_reg 3d100120h ep in c ontrol status register2 out index registers out_csr1_reg 3d100140h ep out control status register1 out_csr2_reg 3d100150h ep out control status register2 out_wrt_cnt1 3d100160h ep out write count register1 out_wrt_cnt2 3d100170h ep out write count register2
usb device S5L840F 16-4 function address register (func_addr_reg) this register maintains the usb device controller address assigned by the host. the mcu writes the value received through a set_address descriptor to this regi ster. this address is used for the next token. register address r/w description reset value func_addr_reg 0x3d100000 r/w function address register 0x00 symbol bit mcu usb description reset value addr_update [7] r/ set r/ clear set by the mcu whenever if updates the func_addr field in the register. this bit will be cleared by usb when data_end bit in ep0_csr register. 0 function_addr [6:0] r/w r the mcu writes the address to these bits 00
S5L840F usb device 16-5 power management register (pwr_mngnt_reg) this register is used for suspend, resume and reset signaling. register address r/w description reset value pwr_mngnt_reg 0x3d100010 r/w power management register 0x00 symbol bit mcu usb description reset value iso_update [7] r/w r used for iso mode only. if set, gfi waits for a sof token to set in_pkt_rdy even though a packet to send is already loaded by mcu. if an in token is received before a sof token, then a zero length data packet will be sent. 0 reserved [6:4] usb_reset [3] r set set by the usb if reset signaling is received from the host. this bit remains set as long as reset signaling persists on the bus. 0 mcu_resume [2] r/w r/ clear set by the mcu for mcu resume. the usb generates the resume signaling during 10ms, if this bit is set in suspend mode. suspend_mode [1] r set/ clear set by usb automatically when the device enter into suspend mode. it is cleared under the following conditions: 1) the mcu clears the mcu_resume bit by 0 suspend_en [0] r/w r suspend mode enable control bit 0 = disable (default) the device will not enter suspend mode 1 = enable suspend mode 0
usb device S5L840F 16-6 interrupt register1 (ep_int_reg) the usb core has two interrupt registers. these registers act as status register s for the mcu when it is interrupted. t he bits are cleared by writing a ?1?(not ?0?) to each bit that was set. once the mcu is interrupted. mcu should read the content s of interrupt-related registers and write back to clear the contents if it is necessary. register address r/w description reset value ep_int_reg 0x3d100020 r/w ep interrupt pending / clear register 0x00 register bit mcu usb description reset value reserved [8:4] ep1~ep3 [3:1] r/ clear set for bulk/interrupt in endpoints : set by the usb under the following conditions: 1. in_pkt_rdy bit is cleared 2. fifo is flushed 3. sent_stall set for bulk/interrupt out endpoints : set by the usb under the following conditions: 1. sets out_pkt_rdy bit 2. sets sent_stall bit 3. for iso in endpoints : set by the usb under the following conditions: 1. under_run bit is set 2. in_pkt_rdy bit is cleared 3. fifo is flushed note : condition 1 and 2 are mutually exclusive for iso out endpoints : set by the usb under the following conditions: 1. out_pkt_rdy bit is set 2. over run bit is set note : condition 1 and 2 are mutually exclusive 0
S5L840F usb device 16-7 ep0 interrupt [0] r/ clear set correspond to endpoint 0 interrupt. set by the usb under the following conditions: 1. out_pkt_rdy bit is set. 2. in_pkt_rdy bit is cleared. 3. sent_stall bit is set. 4. setup_end bit is set. 5. data_end bit is cleared. (it indicates the end of control transfer) 0
usb device S5L840F 16-8 interrupt register2 ( usb_int_reg) register address r/w description reset value usb_int_reg 0x3d100060 r/w usb interrupt pending/clear register 0x00 symbol bit mcu usb description reset value usb reset interrupt [2] r/ clear set set by the usb when it receives reset signaling 0 resume interrupt [1] r/ clear set set by the usb when it receives resume signaling, while in suspend mode. if the resume occurs due to a usb reset, then the mcu is first interrupted with a resume interrupt. once the clocks resume and the se0 condition persists for 3ms, usb reset interrupt will be asserted. suspend interrupt [0] r/ clear set set by the usb when it receives suspend signalizing. the bit is set whenever there is no activity for 3ms on the bus. thus, if the mcu does not stop the clock after the first suspend interrupt, it will continue to be interrupted every 3ms as long as there is no activity on the usb bus by default, this interrupt is disabled. 0 note : if the reset interrupt is occurred, all usb device registers should be re-configured.
S5L840F usb device 16-9 interrupt enable register (ep_ int_en_reg/usb_int_en_reg) corresponding to each interrupt register. the usb devic e controller also has two interrupt enable registers (except resume interrupt enable). by default usb reset interrupt is enabled. if bit = 0, the interrupt is disabled. if bit = 1, the interrupt is enabled. register address r/w description reset value ep_int_en_reg 0x3d100070 r/w determine which interrupt is enabled 0xff symbol bit mcu usb description reset value ep3_int_en [3] r/w r ep3 interrupt enable bit 0 = interrupt disable, 1 = enable 1 ep2_int_en [2] r/w r ep2 interrupt enable bit 0 = interrupt disable, 1 = enable 1 ep1_int_en [1] r/w r ep1 interrupt enable bit 0 = interrupt disable, 1 = enable 1 ep0_int_en [0] r/w r ep0 interrupt enable bit 0 = interrupt disable, 1 = enable 1 register address r/w description reset value usb_int_en_reg 0x3d1000b0 r/w determine which interrupt is enabled 0x04 symbol bit mcu usb description reset value reset_int_en [2] r/w r reset interrupt enable bit 0 = interrupt disable, 1 = enable 1 reserved [1] 0 suspend_int_en [0] r/w r suspend interrupt enable bit 0 = interrupt disable, 1 = enable 0
usb device S5L840F 16-10 frame number register (frame_num1_reg/frame_num2_reg) when the host transfer usb packets, each start of frame(sof) packet includes a frame number. the usb device controller catches this frame number and l oads it into this register automatically. register address r/w description reset value frame_num1_reg 0x3d1000c0 r frame number lower byte register 00 symbol bit mcu usb description reset value frame_num1 [7:0] r w frame number lower byte value 00 register address r/w description reset value frame_num2_reg 0x3d1000d0 r frame number higher byte register 00 symbol bit mcu usb description reset value frame_num2 [7:0] r w frame number higher byte value 00
S5L840F usb device 16-11 dma transfer enable regi ster (dma_en_reg) these registers maintain the number of bytes in the packet as the number is unloaded by the mcu register address r/w description reset value dma_en_reg 0x3d1000f0 r/w dma transfer enable register 00 symbol bit mcu usb description reset value ep3_dma_enable [3] r/w r endpoint 3 dma transfer enable 0 : dma disable 1 : dma enable 00 ep2_dma_enable [2] r/w r endpoint 2 dma transfer enable 0 : dma disable 1 : dma enable 00 ep1_dma_enable [1] r/w r endpoint 1 dma transfer enable 0 : dma disable 1 : dma enable 00 reserved [0]
usb device S5L840F 16-12 index register (index_reg) the index register is used to indicate certain endpoint registers effectively. t he mcu can access the endpoint register (maxp_reg, in_csr1_reg, in_c sr2_reg, out_csr1_r eg, out_csr2_reg, out_wrt_cnt1_reg and out_wrt_cnt2_reg) for an endpoint inside the core using the index register. register address r/w description reset value index_reg 0x3d1000e0 r/w register index register 00 symbol bit mcu usb description reset value index [7:0] r/w r indicate a certain endpoint 00
S5L840F usb device 16-13 endpoint0 control status register (ep0_csr) this register has the control and status bits for endpoint 0. since a control transacti on is involved with both in and out tokens, there is only one csr register, mapped to the in csr1 regist er. (share in1_csr and can access by writing index regist er ?0? and read/write in1_csr) register address r/w description reset value ep0_csr 0x3d100110 r/w endpoint 0 status register 00 symbol bit mcu usb description reset value serviced_setup_ end [7] clear clear the mcu should write a "1" to this bit to clear setup_end. 0 serviced_out_pk t_rdy [6] clear clear the mcu should write a "1" to this bit to clear out_pkt_rdy. 0 send_stall [5] r/w clear mcu should write a ?1? to this bit at the same time it clears out_pkt_rdy, if it decodes and invalid token. 0 = finish the stall condition 1 = the usb issues a stall and shake to the current control transfer 0 setup_end [4] r set set by the usb when a control transfer ends before data_end is set. when the usb sets this bit, an interrupt is generated to the mcu. when such a condition occurs, the usb flushes the fifo and invalidates mcu access to the fifo. 0 data_end [3] set/ r clear set by the mcu on the conditions below : 1. after loading the last packet of data into the fifo, at the same time in_pkt_rdy is set. 2. while it clears out_pkt_rdy after unloading the last packet of data. 3. for a zero length data phase. 0 sent_stall [2] clear /r set set by the usb if a control transaction is stopped due to a protocol violation. an interrupt is generated when this bit is set. the mcu should write ?0? to clear this bit. 0 in_pkt_rdy [1] set/r clear set by the mcu after writing a packet of data into ep0 fifo. the usb clears this bit once the packet has been successfully sent to the clears this bit, so as the mcu to load the next packet. for a zero length data phase, the mcu sets data_end at the same time. 0 out_pkt_rdy [0] r set set by the usb once a valid token is written to the fifo. an interrupt is generated when the usb sets this bit. the mcu clears this bit by writing a ?1? to the serviced_out_ pkt_rdy bit 0
usb device S5L840F 16-14 endpoint in control status 1 register (in_csr1_reg) register address r/w description reset value in_csr1_csr 0x3d100110 r/w in endpoint c ontrol status 1 register 00 symbol bit mcu usb description reset value reserved [7] clr_data_toggl e [6] r r used in set-up procedure. 0 : there are alternation of data0 and data1 1 : the data toggle bit is cleared and pid in packet will maintain data0 0 sent_stall [5] r/ clear set set by the usb when an in token issues a stall handshake, after the mcu sets send_stall bit to start stall handshaking. when the usb issues a stall handshake, in_pkt_rdy is cleared 0 send_stall [4] w/r r 0 : the mcu clears this bit to finish the stall condition. 1 : the mcu issues a stall handshake to the usb. 0 fifo_flush [3] r/w clear set by the mcu if it intends to flush the packet in input-related fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in process, the usb waits until the transmission is complete before fifo flushing. if two packets are loaded into the fifo, only first packet(the packet is intended to be sent to the host) is in_pkt_rdy bit is cleared 0 under_run [2] r/ clear set valid only for iso mode set by the usb when in iso mode, an in token is received and the in_pkt_rdy bit is not set. the usb sends a zero length data packet for such conditions, and the next packet that is loaded into the fifo is flushed. this bit is cleared by writing 0. 0 fifo_not_empty [1] r set indicates there is at least one packet of data in fifo bit[0] = 0, bit[1] = 0 : no packet in the fifo bit[0] = 1, bit[1] = 0 : 1 packet in the fifo (when fifo size is 2x maxp) bit[0] = 1, bit[1] = 1 : 2 packet in the fifo (when fifo size is 2x maxp) or bit[0] = 1, bit[1] = 1 : 1 packet in the fifo (when fifo size is maxp) 0
S5L840F usb device 16-15 in_pkt_rdy [0] r/set clear set by the mcu after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so the mcu can load the next packet. while this bit is set, the mcu will not be able to write to the fifo. if the mcu sets send_stall bit, this bit can not be set. 0 endpoint in control status 2 register (in_csr2_reg) register address r/w description reset value in_csr2_csr 0x3d100120 r/w in endpoint c ontrol status 2 register 20 symbol bit mcu usb description reset value auto_set [7] r/w r if set, whenever the mcu writes maxp data, in_pkt_rdy will automatically be set by the core without any intervention from mcu. if the mcu writes less than maxp data, in_pkt_rdy bit has to be set by the mcu. 0 iso [6] r/w r used only for endpoints whose transfer type is programmable. 1 : configures endpoint to iso mode 0 : configures endpoint to bulk mode 0 mode_in [5] r/w r used only for endpoints whose direction is programmable. 1 : configures endpoint direction as in 0 : configures endpoint direction an out 1 dma_mode [4] w/r r this bit is used only for endpoints whose interface has dma. 1 : dma enable 0 : dma disable 0 reserved [3:0] 0
usb device S5L840F 16-16 endpoint out control status 1 register (out_csr1_reg) register address r/w description reset value out_csr1_csr 0x3d100140 r/w out endpoint c ontrol status 1 register 00 symbol bit mcu usb description reset value clr_data_toggl e [7] r set when the mcu writes a 1 to this bit, the data toggle sequence bit si reset to data0 0 sent_stall [6] r/ clear set set by the usb when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out_token, the mcu clears this bit by writing 0. 0 send_stall [5] r/w r 0 : the mcu clears this bit to end the stall condition handshake, in_pkt_rdy is cleared 1 : the mcu issues a stall handshake to the usb. the mcu clears this bit to end the stall condition handshake, in_pkt_rdy is cleared. 0 fifo_flush [4] r/w clear the mcu writes a 1 to flush the fifo. this bit can be set only when out_pkt_rdy (d0) is set. the packet due to be unloaded by the mcu will be flushed. 0 data_error [3] r r/w valid only in iso mode this bit should be sampled with out_pkt_rdy. when set, it indicates the data packet due to be unloaded by the mcu has an error(either bit stuffing or crc). if two packets are loaded into the fifo, and the second packet has an error, then this bit gets set only after the first packet is unloaded. this bit is automatically cleared when out_pkt_rdy gets cleared. 0 over_run [2] r/ clear r/w valid only in iso mode. this bit is set if the core is not able to load an out iso token into the fifo. mcu clears this bit by writing 0. 0 fifo_full [1] r r/w indicate no more packets can be accepted bit[0] = 0, bit[1] = 0 : no packet in the fifo bit[0] = 1, bit[1] = 0 : 1 packet in the fifo (when fifo size is 2x maxp) bit[0] = 1, bit[1] = 1 : 2 packet in the fifo (when fifo size is 2x maxp) or bit[0] = 1, bit[1] = 1 : 1 packet in the fifo (when fifo size is maxp) 0
S5L840F usb device 16-17 out_pkt_rdy [0] r/ clear set set by the usb after it has loaded a packet of data into the fifo. once the mcu reads the packet from fifo, this bit should be cleared by mcu (write a ?0?) endpoint out control status 2 register (out_csr2_reg) register address r/w description reset value out_csr2_csr 0x3d100150 r/w out endpoint c ontrol status 2 register 00 symbol bit mcu usb description reset value auto_clr [7] r/w r if the mcu is set, whenever the mcu reads data from the out fifo, out_pkt_rdy will automatically be cleared by the logic without any intervention from the mcu 0 iso [6] r/w r determine endpoint transfer type. 0 : configures endpoint to bulk mode 1 : configures endpoint to iso mode default = 0 0 reserved [5:0] r r
usb device S5L840F 16-18 endpoint fifo register (epn_fifo_reg) register address r/w description reset value ep0_fifo 0x3d100200 r/w endpoint0 fifo register xx ep1_fifo 0x3d100210 r/w endpoint1 fifo register xx ep2_fifo 0x3d100220 r/w endpoint2 fifo register xx ep3_fifo 0x3d100230 r/w endpoint3 fifo register xx symbol bit mcu usb description reset value fifo_data [7:0] r/w r/w fifo data value xx
S5L840F usb device 16-19 max packet regisger (maxp_reg) register address r/w description reset value maxp_reg 0x3d100130 r/w endpoint max packet register 00 symbol bit mcu usb description reset value maxp [7:0] r/w r 0000_0000 : maxp = 8 (default value) 0000_0010 : maxp = 16 (endpoint 0) 0000_1000 : maxp = 64 (endpoint 1,2,3) 00
usb device S5L840F 16-20 endpoint out write count regisg er (out_wrt_cnt1/out_wrt_cnt2) these registers maintain the number of bytes in the packet as the number is unloaded by the mcu register address r/w description reset value out_wrt_cnt1 0x3d100160 r/w endpoint out write count register1 00 symbol bit mcu usb description reset value out_cnt_low [7:0] r w lower byte of write count 00 register address r/w description reset value out_wrt_cnt2 0x3d100170 r/w endpoint out write count register1 00 symbol bit mcu usb description reset value out_cnt_high [7:0] r w higher byte of write count 00
chapter 17. iis(tx/rx) module the iis bus transmits pcm audio data to external dac and receives pcm audio data from external adc. to minimize the number of pins r equired and to keep wiring simple, a 3-line serial bus which consists of a data line for time-multi plexed two-channel data(lef t/right), a word select line and a clock line is used. in S5L840F, iis bus has 6 data lines(one for reception and 5 for transmission), 2 word select lines and 2 clock lines(one for reception and the other for transmission). iis has two modes for data transfer. in transmission mode, iis module makes a request for pcm audio data to iodma module and iodma module brings audio data decoded by adm from sdram. in reception mode, iis module gets audio data from external source and stores them into sdram by requesting dma to iodma module. 5 da ta lines are synchronized with 1 word select line and 1 clock line for transmission mode and 1 data line is synchronized with 1 word select line and 1 clock line for reception mode. in iis bus, the chip which generates the bit clock is called master. either transmitter or receiver of audio data has to generate the bit clock and word select clock as a master since they use the same clock signal for data transfer. S5L840F acts only as a master in iis bus, that is, always provides two clock signals(bit clock and word se lect clock) for a slave even when it receives audio data. feature ? 2 data transfer modes ? transmission, reception ? dma mode transfer only ? 5 x 24-bit buffers for transmission and 1 x 24-bit buffer for reception ? 16/20/24 bit data per channel ? up to 10 channels for transmission and 2 channels for reception ? msb-first or lsb-first transfer mode ? iis, left-justified and right-justified format compatible ? burst transfer mode, which makes tx buffer filled by burst length in one request. ? master mode only ? programmable frequency divi der for serial bit clock ? lrck polarity change at both posedge and negedge of serial bit clock ? 32, 48, 64fs(sampling frequency) serial bit clock per frame ( left channel + right channel ) ? 256, 384, 512fs master clock(dac clock)
S5L840F iis 2 block diagram txsclkg brfc data buffer rxsclkg txchnc rxchnc txsftr rxsftr mclk addr data cntl pclk mclk sdo (5 ch) txsclko txlrcko rxsclko rxlrcko sdi (1 ch) cdclk fig 1. iis block diagram z brfc : register bank, apb interface, finite state machine for dma request z txsclkg, rxsclkg : generation of serial bit clock for tx and rx, respectively z data buffer : 24-bit data buffer for tx and rx z txchnc, rxchnc : generation of control signal s which connect data buffer with shift register, data alignment depending on various data transfer mode z txsftr, rxsftr : shift register which transfers parallel data serially
S5L840F iis 3 pin description pin name width i/o description pclk 1 i global clock presetn 1 i global reset apb interface psel 1 i selection in apb penable 1 i enable in apb pwrite 1 i write/read in apb paddr 4 i address in apb pwdata 24 i write data in apb prdata 32 o read data in apb iis interface mclk 1 i audio main clock cdclk 1 o external dac clock txsclko 1 o serial bit clock for transmission txlrcko 1 o word select signal for transmission sdo0 1 o audio data output sdo1 1 o audio data output sdo2 1 o audio data output sdo3 1 o audio data output sdo4 1 o audio data output rxsclko 1 o serial bit clock for reception rxlrcko 1 o word select signal for reception sdi 1 i audio data input dma request dmareqn 2 o dma request signal [tx, rx] dmaackn 2 i dma acknowledge signal [tx, rx]
S5L840F iis 4 registers name width address (virtual) r/w description reset i2sclkcon 32 0x3ca0 0000(0x39 4000) r/w clock control register 0x0000 0002 i2stxcon 32 0x3ca0 0004(0x39 4004) r/w tx configuration register 0x0000 0000 i2stxcom 32 0x3ca0 0008(0x39 4008) r/w tx command register 0x0000 0000 i2stxdb0 32 0x3ca0 0010(0x39 4010) w tx data buffer 0x0000 0000 i2srxcon 32 0x3ca0 0030(0x39 4030) r/w rx configuration register 0x0000 0000 i2srxcom 32 0x3ca0 0034(0x39 4034) r/w rx command register 0x0000 0000 i2srxdb 32 0x3ca0 0038(0x39 4038) r rx data buffer 0x0000 0000 i2sstatus 32 0x3ca0 003c(0x39 403c) r status register 0x0000 000d i2s clock control register (i2sclkcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 i2sclkcon bit description initial state [31:2] reserved 0 i2s clock down ready (read only) [1] 0 = clock-down not ready 1 = clock-down ready 1 i2s power on [0] 0 = power off 1 = power on 0
S5L840F iis 5 i2s tx configuration register (i2stxcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 0 0 1 i2stxcon bit description initial state [31:19] reserved 0 burst mode [18:16] burst length(bl) selection burst length = ( bl[2:0] + 1 ) 0 lrck polarity change [15] 0 = sclk falling edge 1 = sclk rising edge 0 audio interface format [14:13] 0x = iis (basic format) 10 = left justified 11 = right justified 00 msb first or lsb firstin serial interface [12] 0 = msb first (normal audio interface mode) 1 = lsb first 0 left/right channel polarity ( lrck ) [11] 0 = left channel for low polarity 1 = left channel for high polarity 0 [10:8] sclk = mclk / {(3-bit value +1) * 2} 000 4-bit scaler for sclk generation [7] reserved ( always recognized as zero ) 0 serial data bit per channel [6:5] 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = n/a 00 bit clock per frame (frame = left + right) [4:3] 00 = 32 fs 01 = 48 fs 10 = 64 fs 11 = n/a 00 channel index [2:0] channel index=number of channels / 2 (<=5 ) 0
S5L840F iis 6 i2s tx command register (i2stxcom) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 i2stxcom bit description initial state [31:4] reserved 0 tx enable select2 [3] 0 = no transfer 1 = transmit mode on 0 i2s interface enable [2] 0 = i2s interface disable (stop) 1 = i2s interface enable (start) 0 dma service request enable [1] 0 = dma request disable 1 = dma request enable 0 channel idle command [0] 0 = channel not idle ( lrck on ) 1 = channel idle ( lrck off ) 0 i2s data buffer register (i2stxdb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data i2stxdb bit description initial state i2s transmit data [31:0] transmit data to dac 0
S5L840F iis 7 i2s rx configuration register (i2srxcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 1 0 1 0 0 1 i2srxcon bit description initial state [31:13] reserved 0 lrck polarity change [12] 0 = sclk falling edge 1 = sclk rising edge 0 audio interface format [11:10] 0x = iis (basic format) 10 = left justified 11 = right justified 0 msb first or lsb first in serial interface [9] 0 = msb first (normal audio interface mode) 1 = lsb first 0 left/right channel polarity [8] 0 = left channel for low polarity 1 = left channel for high polarity 0 [7:5] sclk = mclk / {(3-bit value+1) * 2} 0 4-bit scaler for sclk generation [4] reserved ( always recognized as zero ) 0 serial data bit per channel [3:2] 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = n/a 0 bit clock per frame (frame = left + right) [1:0] 00 = 32 fs 01 = 48 fs 10 = 64 fs 11 = n/a 0
S5L840F iis 8 i2s rx command register (i2srxcom) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 0 i2srxcom bit description initial state [31:4] reserved 0 rx enable select [3] 0 = no transfer 1 = receive mode on 0 i2s interface enable [2] 0 = i2s interface disable (stop) 1 = i2s interface enable (start) 0 dma service request enable [1] 0 = dma request disable 1 = dma request enable 0 channel idle command [0] 0 = channel not idle ( lrck on ) 1 = channel idle ( lrck off ) 0 i2s rx data buffer register (i2srxdb) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data i2srxdb bit description initial state i2s receive data [31:0] receive data from adc 0
S5L840F iis 9 i2s status register (i2sstatus) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 1 i2sstatus bit description initial state [31:4] reserved 0 rxdbemp [3] rx data buffer state flag 0 = not empty 1 = empty 1 rxlridx [2] rx left/right channel index 0 = left channel 1 = right channel 1 txdbful [1] tx data buffer state flag 0 = not full 1 = full 0 txlridx [0] tx left/right channel index 0 = left channel 1 = right channel 1 iis operations iis clock frequency the main clock of iis(pclk) is the same as system clock whose frequency is 117mhz. audio main clock(mclk) is made by pll2 and is determined considering sampling frequency of audio data. the relationship between sampling frequency(fs) and audio main clock is shown in table 1. serial bit clock(sclk) is determined depending on mclk and data bit per channel(table 2) and is set by the value of configuration register(i2s txcon, i2srxcon). word select signal(lrck) has the same frequency as sampling frequency(fs). lrck (fs) 8.000 khz 11.03 khz 16.00 khz 22.05 khz 32.00 khz 44.10 khz 48.00 khz 64.00 khz 88.20 khz 96.0 khz 256fs mclk 2.048 2.822 4.096 5.645 8.192 11.29 12.29 16.38 22.58 24.58 (mhz) 384fs 3.072 4.234 6.144 8.467 12.29 16.93 18.43 24.58 33.87 36.86 512fs 4.096 5.645 8.192 11.29 16.38 22.58 24.58 32.77 45.16 49.15 table 1. the frequency of audio main clock
S5L840F iis 10 serial bit per channel 16-bit 20-bit 24-bit serial clock frequency (bclk) @codeclk=256fs 32fs, 64fs 32fs, 64fs 32fs, 64fs @codeclk=384fs 32fs, 48fs 32fs, 48fs 32fs, 48fs @codeclk=512fs 32fs, 64fs 32fs, 64fs 32fs, 64fs table 2. the frequency of serial bit clock audio interface format iis-bus format (n=16, 24 or 32) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) lrck bclk iisd left right left msb-justified format (n=16, 24 or 32) 2nd bit lsb (last) lrck bclk iisd left right msb (1st) lsb-justified format (n=16, 24 or 32) n-1th bit lsb (last) lrck bclk iisd left right msb (1st) 0 2nd bit lsb (last) 0 msb (1st) 0 n-1th bit lsb (last) msb (1st) 0 fig 2. audio data interface format in S5L840F, iis module is applicable to various in terface format as shown above. iis-bus format starts data transfer at the next bclk clock afte r word select signal(lrck) changes the polarity. but msb-justified format transfers data from the very clock that lrck changes the polarity. lsb- justified format completes one channel transfer at the same time as the change of lrck. if there exists more serial clock bits in one channel th an serial data bits, the remaining clock bits are stuffed with zero?s in each case.
S5L840F iis 11 depending on register values, msb of audio data or lsb can be transferred first and data transfer can be synchronized with the rising edge or falling edge of lrck. start and stop condition to make iis module active, i2s_power_on bit in i2 sclkcon must be set to ?1?. after iis module becomes active, setting command register to ?0x0000 000e? drives iis to its function mode. iis_interface_enable bit in command register decides the generation of serial bit clock(sclk) and makes iis bus stop immediately after it is set to ?0?. iis_channel_idle_command bit decides the generation of word select signal(lrck) and makes iis transfer one pair datum after it is set to ?0? and then makes it stop. therefore, iis_interface_enable bit can be used to refresh current sdram data and iis_channel_idle_command bit be used to maintain current sdram data. to make iis inactive, the procedure is as follows. 1. set i2s_power_on to ?0?. 2. wait until i2s_power_down_ready becomes set to ?1?. dma data transfer iis module gives audio data to memory or gets from memory through iodma module. therefore, iis module sends the request signal to iodma module for audio data and receives acknowledgement signal after the completion of data transfer. both request and acknowledgement signal have 2 bits, one for transmission and the other for reception. for transmission, iis module sends request signal when tx data buffers are not occupied and receives acknowledgement signal after it receiv es audio data by burst length. since iis module acquires audio data by burst length per request and acknowledgement counter also increases by burst length per request, burst mode bit in i2stxcon must be set with the same burst length as in iodma module to increase acknowledgement counter correctly. if acknowledgement counter is less than the number of channels, that is, data buffer is not full after one request, iis module sends request signal until data_buffer_full flag becomes set to ?1?. after data_buffer_full flag is set to ?1?, internal signal which indicates the start of next channel transfers audio data in buffers into tx shift registers and resets data_buffer_full flag to ?0?. for reception, the data buffer is empty at first(buffer_empty flag = ?1?). the audio data are received into rx shift register and is transferred to data buffer with the internal channel_start signal. after the buffer_empty flag becomes set to ?0?, iis module sends request signal for rx to iodma and then receives acknowledgement signal after audio data in data buffer is read. data reception is independent of data transmission and therefore the two modes can function simultaneously. program guide of rx mode iis module is consist of iis rx part and tx part. each part has iis interface signals (lrck, bck, adata). and we support only master mode of iis rx. so S5L840F share two pin lrck, bck. as this restriction, there is some problem of receiving wrong data. this is a program guide to use rx mode. 1. dma channel 0 set (iis tx channel) dmabase0, dmacon0, dmatcnt 0, dmacom0 registers set 2. dma channel 1 set (iis rx channel) dmabase0, dmacon0, dmatcnt 0, dmacom0 registers set 3. iis rx mode set ( you must set rx mode first and then set tx mode )
S5L840F iis 12 i2srxcon register set 4. iis tx mode set i2stxcon register set 5. iis rx clock on i2srxcom register set 6. iis tx clock on i2stxcom register set
chapter 18. iic module S5L840F has a multi-master iic-bus serial inte rface. a dedicated serial data line (sda) and a serial clock line (scl) carry information between bus masters and peripheral devices that are connected to the iic-bus. the sda and scl lines are bi-directional. to control multi-master iic-bus operations, values must be written to the following registers. ? multi-master iic-bus co ntrol register, iiccon ? multi-master iic-bus control/status register, iicstat ? multi-master iic-bus tx/rx data shift register, iicds ? multi-master iic-bus address register, iicadd when the iic-bus is free, the sda and scl lines should be both at high level. a high-to-low transition of sda line initiates a start condition while scl line remains at high level. a low-to-high transition of sda line with scl line high gener ates a stop condition with scl line high. the start and stop condition should always be generated by the master devices. a 7-bit address value in the first data transfer, which is put onto the bus after the start condition, determines the slave device that is addressed by the 7-bit address. the 8 th bit in the first data transfer determines the direction of the tra nsfer (read or write). every data onto the sda line should be eight bits or one byte. the number of bytes that can be transferred during the bus transfer is unlimited. data is always sent from the msb bit and acknowledge (ack) bit should be asserted after one byte transfer. 1 feature ? four operation mode ? master transmitter mode ? master receive mode ? slave transmitter mode ? slave receive mode ? configurable slave address ? operation pending until the interrupt pending flag is cleared by the software 1 this is dependent on the devices. some other devices, for example eeprom, need not to generate ack signals.
S5L840F iic 2 block diagram iic-bus control logic iiccon iicstat 4-bit prescaler shift register iicds shift register comparator address register sda scl apb fig 1. iic block diagram pin description pin name width i/o description gclk 1 i global clock presetn 1 i global reset apb interface psel 1 i selection in apb penable 1 i enable in apb pwrite 1 i write/read in apb paddr 6 i address in apb pwdata 8 i write data in apb prdata 32 o read data in apb iic interface sclin 1 i iic clock line input sdain 1 i iic data line input sclout 1 o iic clock line output sdaout 1 o iic data line output interrupt interface intc 1 o interrupt gclk apb clock (main clock) presetn global reset to reset the internal register apb interface signals (psel, penable, pwrite, paddr, pwdata, prdata) amba apb interface signals sclin
S5L840F iic 3 iic clock input line. sdain iic data input line sclout iic clock output line sdaout iic data output line intc interrupt signal. registers name width address(virtual) r/w description reset iiccon 32 0x3c90 0000(0x39 2000) r/w control register 0x0000 000x iicstat 32 0x3c90 0004(0x39 2004) r/w control/status register 0x0000 0000 iicadd 32 0x3c90 0008(0x39 2008) r/w bus address register - iicds 32 0x3c90 000c(0x39 200c) r/w transmit/receive data shift register -
S5L840F iic 4 multi-master iic-bus control register (iiccon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name type description reset 7 acknowledge generation (ack_gen) r/w iic-bus acknowledge enable bit 0 1 disable enable in tx mode, the iicsda is free in the ack time. in rx mode, the iicsda is low in the ack time. 0 6 tx clock source selection (cksel) r/w source clock of iic-bus transmit clock pre-scaler selection bit 0 1 iicclk = pclk / 16 iicclk = pclk / 512 0 5 tx/rx interrupt (int_en) r/w iic-bus tx/rx interrupt enable/disable bit 0 1 disable enable 0 4 interrupt pending flag 1 (irq) r/w iic-bus tx/rx interrupt pending flag. read operation 0 1 no interrupt pending interrupt is pending. in this condition, the iicscl is tied to low and the iic is stopped. write operation 0 1 nothing occurs clear the pending condition and resume the operation 0 3:0 transmit clock value (ck_reg) r/w iic-bus transmit clock prescaler iic-bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formular: tx clock = iicclk / (iiccon[3:0] + 1) - shuld be ck_reg[3:0] > 0 - -ck_reg[3:0] ? ?? 0 ?? ??? ?? scl ? ????? ????? sda ? ?? 0 ?? ??? ?? . ??? 0 ??? ?? ???? ?? . - slave mode ??? ck_sel, ck_reg ?? master ? ?? ??? ?????? ??? ? => slave ??? clock ?? ?? ?? ??? ?? . 1 an iic-bus interrupt occurs - when one-byte transmit or receive operation is completed - when a general call or a slave address match occurs - if bus arbitration fails
S5L840F iic 5 multi-master iic-bus control/status register (iicstat) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits name type description reset 7:6 mode selection (mode_sel) r/w iic-bus master/slave tx/rx mode selection 00 01 10 11 slave receive mode slave transmit mode master receive mode master transmit mode 0 5 busy signal status/ start-stop generation (bb) r/w read operation: iic-bus busy signal status bit 0 1 not busy busy write operation: start-stop signal generation 0 1 stop signal generation start signal generation 0 4 serial output (soe) r/w iic-bus data output enable/disable bit 0 1 disable tx/rx enable tx/rx 0 3 arbitration status flag (lba) r iic-bus arbitration procedure status flag 0 1 bus arbitration successful bus arbitration failed during serial i/o 0 2 address-as-slave status flag (aas) r iic-bus address-as-slave status flag 0 1 when start/stop condition was detected received slave address matches the address value in the iicadd 0 1 address zero status flag (addr_zero) r iic-bus address zero status flag 0 1 when start/stop condition was detected received slave address is 00000000b 0 0 last received bit status flag (lrb) r iic-bus last received bit status flag 0 1 last received bit is 0 (ack was received) last received bit is 1 (ack was not received) 0 % i2c ? 1byte ? ??? ack ? ?? ?? ?? interrupt ? ?? ??? . ? interrupt ????? scl ? low ? ?? ??? bus ? ?? ?? ??? . % ?? i2c device ? default ? ?0? slave address ? ack ? ????? ??? ?? ??? master ? ??? ?? i2c slave ? ??? ?? write ??? ?? ???? .
S5L840F iic 6 multi-master iic-bus address register (iicadd) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s_addr bits name type description reset 7:1 slave address (s_addr) r/w 7-bit slave address. when serial output is disabled, iicadd is writable. slave address = iicadd[7:1] - - iicadd ? ?? ??? slave address ? ?? ???? serial output ? ??? disable ???? ?? . ??? serial output ? enable ?? ?? slave address ? ??? ?? ??? ?? ??? ?? reset ??? ??? ?0? ? ?? ???? . multi-master iic-bus transmit /receive register (iicds) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data bits name type description reset 7:0 data shift (data) r/w 8-bit data shift register for iic-bus tx/rx operation: when serial output is enabled, iicds is writable. - - serial output ? enable ???? iicds ? ?? ???? ?? . ??? ??? iicds ? ?? ??? ??? unkown ?? sda ? ??? ?? . iic operation iic clock frequency pclk cksel ck_reg = 0 ck_reg = 15 pclk / 16 7.593 mhz 474 khz 121.5 mhz pclk / 512 237 khz 14 khz in S5L840F, the main clock is 121.5 mhz. so the available operation frequency of iic is as shown in the above table. user can adjust the operation frequency by the ck_reg field in the iiccon register. start and stop condition when the iic-bus interface is inactive, it is usually in slave mode. in other words, the interface should be in slave mode before detecting a start condition on the sda line (a start condition can be initiated with a high-to-low transition of the sda line while the clock signal of scl is high). when the interface state is changed to master mode, a data transfer on the sda line can be initiated and scl signal generated.
S5L840F iic 7 a start condition can transfer one-byte serial data over the sda line, and a stop condition can terminate the data transfer. a stop condition is a low-to-high transition of the sda line while scl is high. start and stop conditions are always generated by the master. the iic-bus gets busy when a start condition is generated. a stop condition will make the iic-bus free. when a master initiates a start condition, it should send a slave address to notify the slave device. one byte of address field consists of a 7-bit address and a 1-bit transfer direction indicator (showing write or read). if bit 8 is 0, it indicates a write operation (transmi t operation); if bit 8 is 1, it indicates a request for data read (receive operation). the master will finish the transfer operation by tr ansmitting a stop condition. if the master wants to continue the data transmission to the bus, it should generate another start condition as well as a slave address. in this way, the read-write operation can be performed in various formats. scl sda sda scl start condition stop condition figure 2. start and stop condition data transfer format every byte placed on the sda line should be eight bits in length. the bytes can be unlimitedly transmitted per transfer. the first byte following a start condition should have the address field. the master can transmit the address field when the iic-bus is operating in master mode. each byte should be followed by an acknowledgement (ack) bit. the msb bit of the serial data and addresses are always sent first.
S5L840F iic 8 notes: 1. s : start, rs: repeat start, p : stop, a: acknowledge 2. : from master to slave, : from slave to master write mode format with 7-bit addresses "0" (write) data transferred (data + acknowledge) s slave address 7bits r/w a p data(1byte) a read mode format with 7-bit addresses "1" (read) data transferred (data + acknowledge) s slave address 7 bits r/w a p data a write mode format with 10-bit addresses "0" (write) data transferred (data + acknowledge) p data a s slave address 1st 7 bits r/w a slave address 2nd byte a 11110xx read mode format with 10-bit addresses "1" (read) s slave address 1st 7 bits 11110xx r/w a slave address 2nd byte a rs slave address 1st 7 bits a data transferred (data + acknowledge) p data a r/w "1" (read) figure 3. iic-bus interface data format % restart ? scl ? low ?? start ? ???? restart ? ?? . ? ??? scl ? high ??? ?? ??? ?? ?? ?? ???? ?? start bit ? 1 ? write ?? start ? ?? ??? ??? ?? ?? (scl low) ?? ?? start bit ? 1 ? write ?? restart ? ?? .
S5L840F iic 9 sda acknowledgement signal from receiver scl s 1 2 789 12 9 acknowledgement signal from receiver msb ack byte complete, interrupt within receiver clock line held low by receiver and/or transmitter figure 4. data transfer on the iic-bus ack signal transmission to complete a one-byte transfer operation, the re ceiver should send an ack bit to the transmitter. the ack pulse should occur at the ninth clock of the scl line. eight clocks are required for the one-byte data transfer. the master should generate the clock pulse required to transmit the ack bit. the transmitter should release the sda line by making the sda line high when the ack clock pulse is received. the receiver should also drive the sda line low during the ack clock pulse so that the sda keeps low during the high period of the ninth scl pulse. the ack bit transmit function can be enabled or di sabled by software (iicstat). however, the ack pulse on the ninth clock of scl is required to complete the one-byte data transfer operation. data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment clock to output 9 8 7 s 1 2 figure 5. acknowledge on the iic-bus
S5L840F iic 10 read-write operation in transmitter mode, when the data is transferred, the iic-bus interface will wait until iic-bus data shift (iicds) register receives a new data. before the new data is written to the register, the scl line should be held low, and then released after it is written. the iic controller should hold the interrupt to identify the completion of current data transfer. after the cpu receives the interrupt request, it should write a new data into the iicds register, again. in receive mode, when a data is received, the iic -bus interface will wait un til iicds register is read. before the new data is read out, the scl line will be held low and then released after it is read. the iic controller should hold the interrupt to identify the completion of the new data reception. after the cpu receives the interrupt r equest, it should read the data from the iicds register. -master ? 7bit ????? slave ?? ??? 8 ?? bit ?? r/w ??? ?? slave ? ? r/w ??? ??? transmit or receive mode ? ??? ?? ?? . ? master ? slave ? transmit or receive ? ?? ?? ?? . bus arbitration procedures arbitration takes place on the sda line to prevent the contention on the bus between two masters. if a master with a sda high level detects the other master with a sda active low level, it will not initiate a data transfer because the current level on the bus does not correspond to its own. the arbitration procedure will be extended until the sda line turns high. however, when the masters simultaneously lower the sda line, each master should evaluate whether or not the mastership is allocated to itself. for the purpose of evaluation, each master should detect the address bits. while each master generates the slaver address, it should also detect the address bit on the sda line because the sda line is likely to get low rather than to keep high. assume that one master generates a low as first address bit, while the other master is maintaining high. in this case, both masters w ill detect low on the bus because the low status is superior to the high status in power. when this happens, low (as the first bit of address) generating master will get the mastership while high (as the firs t bit of address) generating master should withdraw the mastership. if both masters generate low as the first bit of address, there should be arbitration for the second address bit, again. this arbitration will continue to the end of last address bit. abort conditions if a slave receiver cannot acknowledge the confirmation of the slave address, it should hold the level of the sda line high. in this case, the master should generate a stop condition and to abort the transfer. if a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ack after the last data byte received from the slave. the slave transmitter should then release the sda to allow a master to generate a stop condition. configuring iic-bus to control the frequency of the serial clock (scl), the 4-bit prescaler value can be programmed in the iiccon register. the iic-bus interface address is stored in the iic-bus address (iicadd) register. (by default, the iic-bus interface address has an unknown value.)
S5L840F iic 11 flowcharts of operations in each mode the following steps must be executed before any iic tx/rx operations. 1) write own slave address on iicadd register, if needed. 2) set iiccon register a) enable interrupt b) define scl period 3) set iicstat to enable serial output write slave address to iicds. write 0xf0 (m/t start) to iicstat. the data of the iicds is transmitted. ack period and then interrupt is pending. write 0xd0 (m/t stop) to iicstat. write new data transmitted to iicds. stop? clear pending bit to resume. the data of the iicds is shifted to sda. start master tx mode has been configured. (write 0xc0 to iicstat) clear pending bit. wait until the stop condition takes effect. end y n figure 6. operations for master/transmitter mode
S5L840F iic 12 write slave address to iicds. write 0xb0 (m/r start) to iicstat. the data of the iicds (slave address) is transmitted. ack period and then interrupt is pending. write 0x90 (m/r stop) to iicstat. read a new data from iicds. stop? clear pending bit to resume. sda is shifted to iicds. start master rx mode has been configured. (write 0x80 to iicstat) clear pending bit. wait until the stop condition takes effect. end y n figure 7. operations for master/receiver mode
S5L840F iic 13 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds (the received slave address). write data to iicds. the iic address match interrupt is generated. clear pending bit to resume. the data of the iicds is shifted to sda. start slave tx mode has been configured. (write 0x50 to iicstat) end matched? n y stop? interrupt is pending. n y figure 8. operations for slave/transmitter mode
S5L840F iic 14 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds (the received slave address). read data to iicds. the iic address match interrupt is generated. clear pending bit to resume. sda is shifted to iicds. start slave rx mode has been configured. (write 0x10 to iicstat) end matched? n y stop? interrupt is pending. n y figure 9. operations for slave/receiver mode
spi preliminary spec version 0.1 aug. 29, 2003 byeong-woo jeon media player p/t system lsi division device solution network
S5L840Fx spi 2 contents spi ............................................................................................................................ ......................................... preliminary spec ............................................................................................................... .................. 1 revision history........................................................................................................................ ............. 3 o verview ............................................................................................................................... ......................... 3 f eature ............................................................................................................................... ........................... 4 b lock d iagram ............................................................................................................................... .............. 4 p in d escription ............................................................................................................................... .............. 5 r egisters ............................................................................................................................... ......................... 6 spi o perations ............................................................................................................................... ............. 11
S5L840Fx spi 3 revision history date version number update contents 2003.08.29 0.1 initial version overview spi(serial peripheral interface) in S5L840Fx can transfer serial data with various peripherals. spi has two 8bit shift registers for transmission and reception, respectively. during an transfer, spi receives 8bit serial data at the same time as it transmits at a frequency determined by prescaler register setting. if you want only to transmit data through spi, you may treat the received data as dummy. on the contrary, if you want only to receive data, you should write dummy ?0xff? data to tx buffer since transmission and reception happen at the same time. there are 4 i/o pins associated with spi transfer : an spi clock pin(sck), an miso(master_in_slave_out) data pin, an mosi(master_out_slave_in) data pin and an active low /nss pin. sck, miso and mosi pins act as inputs or outputs depending on register setting and are stitched in the pad module using associat ed signals from spi module. /nss input pin indicates that the spi module is used as a slave by an external master.
S5L840Fx spi 4 feature ? spi protocol(ver. 2.11) compatible ? 2 8-bit shift registers for transmission and reception ? 10-bit prescaler logic ? polling, interrupt and dma transfer mode ? master and slave mode ? 4 combinations of clock polarity and clock phase block diagram apb_if prescaler int_dma count shift register pin logic apb pclk master baud rate spi clock cpol cpha 8-bit data dmareq dmaack int dma mode master clock master slave master slave slave master sck mosi miso fig 1. spi block diagram z apb_if : register bank, interrupt generation z int_dma : dma request z prescaler : generation of prototype spi clock from pclk z count : generation of spi clock depending on clock mode, clock count z shift register : 2 8-bit shift registers for transmission and reception z pin logic : generation of signals needed to make 3 basic spi pins
S5L840Fx spi 5 pin description pin name width i/o description pclk 1 i global clock presetn 1 i global reset apb interface psel 1 i selection in apb penable 1 i enable in apb pwrite 1 i write/read in apb paddr 3 i address in apb pwdata 12 i write data in apb prdata 12 o read data in apb spi interface mi 1 i data input for master mode si 1 i data input for slave mode cki 1 i clock input for slave mode nssi 1 i active low signal indicating whether spi module is slave or not mo 1 o data output for master mode nen_mo 1 o data output enable for master mode so 1 o data output for slave mode nen_so 1 o data output enable for slave mode cko 1 o clock output for master mode nen_cko 1 o clock output enable for master mode dma request & interrupt ndreq 1 o active low dma request signal ndack 1 i active low dma acknowledgement signal int_spi 1 o interrupt of spi module 3 basic spi pins(mosi, miso, sck) are organized as follows in pad module using signals above. mosi nen_mo mo si nen_so so mi nen_cko cko cki miso sck
S5L840Fx spi 6 registers base address : 0x3cd0_0000 (in 32bit), 0x39_a000 (in 24bit) name width address r/w description reset 32 spclkcon 24 base + 00h r/w clock control register 0x0000 0002 32 spcon 24 base + 04h r/w control register 0x0000 0000 32 spsta 24 base + 08h r/w status register 0x0000 0001 32 sppin 24 base + 0ch r/w pin control register 0x0000 0000 32 sptdat 24 base + 10h r/w tx data register 0x0000 0000 32 sprdat 24 base + 14h r rx data register 0x0000 0000 32 sppre 24 base + 18h r/w baud rate prescaler register 0x0000 0000 spi clock control register (spclkcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spclkcon bit description initial state [31:2] reserved 0 spi clock down ready (read only) [1] 0 = clock-down not ready 1 = clock-down ready 1 spi power on [0] 0 = power off 1 = power on 0
S5L840Fx spi 7 spi control register (spcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spcon bit description initial state [31:10] reserved 0 interrupt enable (data collision error) [10] 0 = interrupt masked 1 = interrupt enable 0 interrupt enable (multi master error) [9] 0 = interrupt masked 1 = interrupt enable 0 interrupt enable (transfer ready) [8] 0 = interrupt masked 1 = interrupt enable 0 dma direction [7] 0 = tx dma 1 = rx dma 0 spi mode select [6:5] determine how sptdat/sprdat is written/read 00 = polling mode 01 = interrupt mode 10 = dma mode 11 = reserved 00 spi clock enable [4] spi clock enable (master) or not (slave) 0 = disable 1 = enable 0 master or slave mode [3] 0 = slave mode 1 = master mode note : in slave mode, set-up time is required for master to initiate tx/rx 0 clock polarity select [2] select an active high or active low clock 0 = active high 1 = active low 0 clock phase select [1] this bit selects one of two fundamentally different transfer formats. 0 = first clock edge missing 1 = last clock edge missing 0 tx auto garbage data mode enable (tagd) [0] this bit decides whether receiving data automatically transmits dummy 0xff data or not. when you only want to receive data, you don?t have to transmit dummy 0xff data if this bit is set. 0 = normal mode 1 = tx auto garbage data mode 0
S5L840Fx spi 8 spi status register (spsta) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spsta bit description initial state [31:4] reserved 0 interrupt status bit (data collision error) [3] 0 = no interrupt 1 = interrupt pending ( this interrupt is generated if sptdat is written or sprdat is read while transfer is in progress. this bit can be reset by writing ?1? . writing ?0? has no effect. ) 0 interrupt status bit (multi master error) [2] 0 = no interrupt 1 = interrupt pending ( this interrupt is generated if nss signal goes to low while spi is configured as a master and enmul bit of sppin register is set. this bit can be reset by writing ?1? . writing ?0? has no effect. ) 0 interrupt status bit (transfer ready) [1] 0 = no interrupt 1 = interrupt pending ( this interrupt is generated if transfer ready flag is high in the state of interrupt mode. this bit can be reset by writing ?1?. writing ?0? has no effect. ) 0 transfer ready flag (read only) [0] this flag indicates that sptdat or sprdat is ready to transmit or receive. it is automatically cleared by writing data to sptdat. 0 = not ready 1 = data tx/rx ready 1
S5L840Fx spi 9 spi pin control register (sppin) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sppin bit description initial state [31:4] reserved 0 nssi pin enable [3] this bit determine whether to use nssi pin or not 0 = don?t use (slave condition : mstr bit is off) 1 = use (slave condition : mstr bit is off and nssi is low) 0 multi master error detect enable [2] this bit enables multi master error flag of spsta to be set when multi master error occurs. 0 = disable (general purpose) 1 = multi master error detect enable 0 [1] reserved 0 master out keep [0] determine whether state is kept or released in mosi when 1 byte transfer is finished. (only master) 0 = release 1 = keep the state 0 spi tx data register (sptdat) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sptdat bit description initial state [31:8] reserved 0 tx data [7:0] this field contains the data to be transmitted over spi channel 0
S5L840Fx spi 10 spi rx data register (sprdat) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sprdat bit description initial state [31:8] reserved 0 rx data [7:0] this field contains the data to be received over spi channel 0 spi baud rate prescaler (sppre) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sppre bit description initial state [31:8] reserved 0 prescaler value [9:0] determines spi clock rate with the following equation. baud rate = pclk / ( 2 * ( prescaler value +1 )) 0
S5L840Fx spi 11 spi operations spi transfer format spi has 4 transfer formats depending on cpol and cpha values in spcon register. spi generates clock only when spi transfers or receives data. cpha indcates whether spiclk has a leading edge of the first clock ( cpha = 1 ) or trailing edge of the last clock( cpha = 0 ). cpol determines the polarity of spiclk when spi bus is idle. 1 2 3 4 5 6 7 8 msb654321lsb msb 65 43 2 1lsb cycle spiclk mosi miso msb cpol= 0 , cpha = 0 (format a) 1 2 3 4 5 6 7 8 msb654321lsb msb 65 43 2 1lsb cycle spiclk mosi miso cpol= 0 , cpha = 1 (format b) 1 2 3 4 5 6 7 8 msb654321lsb msb 65 43 2 1lsb cycle spiclk mosi miso msb cpol= 1 , cpha = 0 (format c) 1 2 3 4 5 6 7 8 msb654321lsb cycle spiclk mosi miso cpol= 1 , cpha = 1 (format d) msb 65 43 2 1lsb msb fig. 1. spi transfer format
S5L840Fx spi 12 spi operation using the spi operation, 8-bit data can be sent to and received from external device simultaneously. a serial clock line synchronizes shifti ng and sampling of the data on the two serial data line. when spi acts as a master, transmission frequency can be controlled by setting the appropriate bit to sprpe register . you can modify its frequency to adjust the baud rate data register value. when spi acts as a slave, the ot her master supplies the clock. spi starts its operation as soon as a byte data is written to sptdat register. if 0 th bit of spcon is set, reading sprdat register makes data transfer start without needing to write 8?hff to sptdat. programming procedure when a byte data is written to the sptdat register, spi starts to transmit data if clock-enable bit and master-slave bit of spcon reginster are set. to operate spi module, refer to the following steps. 1. set baud rate prescaler register(sppre). 2. set spcon to configure spi module properly 3. set the gpio pin which acts as nss of external spi device to low to make external spi device slave. 4. to transmit data, check the status of transfer ready flag of spsta register is high and then write data to sptdat. 5. to receive data, if 0 th bit of spcon (tagd) is inactive, write 8?hff to sptdat register, confirm redy to set and then read data from sprdat register. if tagd bit is active, confirm redy to set and then read data from sprdat register. in this case, there is no need to write data to sptdat. 6. set the gpio pin which acts as nss to high to deactivate external spi device. steps for dma mode transmission 1. configure spi as dma mode. 2. the spi requests dma service. 3. dma transmits 1 byte data to the spi. 4. the spi transmits data to external spi module 5. go to step 2 until dma count is 0. 6. the spi is configured as interrupt or polling mode. steps for dma mode reception 1. configure spi as dma mode and set tagd bit to high 2. the spi receives 1 byte data from external spi module. 3. the spi requests dma service. 4. dma receives the data from the spi. 5. write data 8?hff automatically to sptdat. 6. go to step 4 until dma count is 0. 7. the spi is configured as polling mode and tagd bit is cleared. 8. when redy flag of spsta register is set, read the last byte data. note : total received data = dma tc values + the last datum received in polling mode (step 9) the first received datum is dummy, so user may neglect that.
spdif preliminary spec version 0.1 aug. 29, 2003 byeong-woo jeon media player pt system lsi division device solution network
S5L840Fx spdif 2 contents spdif .......................................................................................................................... .................................... 1 preliminary spec ............................................................................................................... .................. 1 revision history........................................................................................................................ ............. 3 o verview ............................................................................................................................... ......................... 3 f eature ............................................................................................................................... ........................... 3 b lock d iagram ............................................................................................................................... .............. 4 p in d escription ............................................................................................................................... .............. 5 r egisters ............................................................................................................................... ......................... 6 spdif o perations ............................................................................................................................... ........ 10
S5L840Fx spdif 3 revision history date version number update contents 2003.08.29 0.1 initial version overview this standard describes a serial, un-directional, self-clocking interface for the interconnection of digital audio equipment for consumer and professional applications. when used in a consumer digital processing environment, the interface is primarily intended to carry stereophonic programs, with a resolution of up to 20 bits per sample, an extension to 24 bits per sample being possible. when used in a broadcasting studio environment, the interface is primarily intended to carry monophonic or stereophonic programs, at a 48khz sampling frequency and with a resolution of up to 24 bits per sample; it may alternatively be used to carry one or two signals sampled at 32 khz. in both cases, the clock references and auxiliary information are transmitted along with the program. provision is also made to allow the interface to carry data related to computer software. feature ? spdif module only supports the consumer application in S5L840Fx. ? linear pcm up to 24-bit per sample is supported. ? non-linear pcm formats such as ac3, mpeg1 and mpeg2 are also supported. ? 2 x 24-bit buffers which is alternately filled with data
S5L840Fx spdif 4 block diagram spdif_tx out_spdif apb interface apb spdif dma interface audio_if_core clock generator fig 1. spdif block diagram z apb interface block : defines register banks to control the driving of spdif module and data buffers to store linear or non-linear pcm data. z dma interface block : requests dma service to iodma depending on the status of data buffer in apb interface block z clock generator block : makes 128fs(sampling frequency) clock used in out_spdif block from system audio clock(mclk) z audio_if_core block : acts as interface block between data buffer and out_spdif block. finite-state machine controls the flow of pcm data. z spdif_tx block : inserts burst preamble and executes zero-stuffing in the nonlinear pcm stream. linear pcm data are bypassed by spdif_tx module. z out_spdif block : makes spdif format. it inserts 4-bit preamble, 16- or 20- or 24-bit data, user-data bit, validity bit, channel status bit and parity bit into the appropriate position of 32-bit word. it modulates each bit to bi-phase format.
S5L840Fx spdif 5 pin description pin name width i/o description pclk 1 i global clock i-dac-clock 1 i global audio main clock presetn 1 i global reset apb interface psel 1 i selection in apb penable 1 i enable in apb pwrite 1 i write/read in apb paddr 3 i address in apb pwdata 32 i write data in apb prdata 32 o read data in apb spdif interface o-spdif-data 1 o spdif data output dma request & interrupt ndmareq 1 o active low dma request signal ndmaack 1 i active low dma acknowledgement signal spdif-int 1 o interrupt of spdif module
S5L840Fx spdif 6 registers base address : 0x3cb0_0000 (in 32bit), 0x39_6000 (in 24bit) name width address r/w description reset 32 spdclkcon 24 base + 00h r/w clock control register 0x0000 0002 32 spdcon 24 base + 04h r/w control register 0x0000 0020 32 spdbstas 24 base + 08h r/w burst status register 0x0000 0000 32 spdcstas 24 base + 0ch r/w channel status register 0x2000 8000 32 spddat 24 base + 10h w spdif data buffer 0x0000 0000 32 spdcnt 24 base + 14h r/w repetition count register 0x0000 0000 spdif clock control register (spdclkcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spclkcon bit description initial state [31:2] reserved 0 spdif clock down ready (read only) [1] 0 = clock-down not ready 1 = clock-down ready 1 spdif power on [0] 0 = power off 1 = power on 0
S5L840Fx spdif 7 spdif control register (spdcon) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spdcon bit description initial state [31:9] reserved 0 data buffer empty flag (read only) [8] 0 = not empty 1 = empty 1 interrupt status bit [7] 0 = no interrupt pending 1 = interrupt pending ( interrupt status bit can be reset by writing ?1? to this bit. writing ?0? to interrupt status bit has no effect. ) 0 interrupt enable bit [6] 0 = interrupt masked 1 = interrupt enable 0 software reset bit [5] 0 = normal operation 1 = software reset 0 main audio clock frequency [4:3] 00 = 256fs 01 = 384fs 10 = 512fs 11 = reserved 0 pcm data size [2:1] 00 = 16 bit 01 = 20 bit 10 = 24 bit 11 = reserved 0 pcm or stream [0] 0 = stream 1 = pcm 0
S5L840Fx spdif 8 spdif burst status register (spdbstas) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spdbstas bit description initial state burst data length bit [31:16] es size in bits ( burst preamble pd ) 0 bitstream number [15:13] bit_stream_number, shall be set to 0 0 data type dependent info [12:8] data type dependent information 0 error flag [7] 0 = error flag indicating a valid burst_payload 1 = error flag indicating that the burst payload may contain errors 0 [6:5] reserved 0 compressed data type [4:0] 0000 = pause data 0001 = ac-3 0010 = mpeg1 ( layer1 ) 0011 = mpeg1 ( layer2, 3 ), mpeg2-bc 0100 = mpeg2 ? extension 0101 = mpeg2 ( layer1 ? lsf ) 0110 = mpeg2 ( layer2, layer3 ? lsf ) others = reserved 0
S5L840Fx spdif 9 spdif channel status register (spdcstas) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spdcstas bit description initial state [31:30] reserved 0 clock accuracy [29:28] 10 = level i, 50 ppm 00 = level ii, 1000 ppm 01 = level iii, variable pitch shifted 10 sampling frequency [27:24] 0000 = 44.1 khz 0100 = 48 khz 1100 = 32 khz 0 channel number [23:20] bit 20 is lsb 0 source number [19:16] bit 16 is lsb 0 category code [15:8] equipment type cd player = 1000_0000 dat player = 1100_000l dcc player = 1100_001l mini disc = 1001_001l (l : information about generation status of the material) 80 channel status mode [7:6] 00 = mode 0 others = reserved 0 emphasis [5:3] 000 = emphasis not indicated 100 = emphasis ? cd type 0 copyright assertion [2] 0 = copyright 1 = no copyright 0 audio sample word [1] 0 = linear pcm 1 = non-linear pcm 0 channel status block [0] 0 = consumer format 1 = professional format 0
S5L840Fx spdif 10 spdif data buffer (spddat) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spddat bit description initial state [31:24] reserved 0 spdif data [23:0] pcm or stream data 0 spdif repetition count register (spdcnt) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spdcnt bit description initial state [31:13] reserved 0 stream repetition count [12:0] repetition count according to data type this bit is valid only for stream data. 0
S5L840Fx spdif 11 data format of spdif frame format a frame is uniquely composed of two sub-frames. the transmission rate of frames corresponds exactly to the source sampling frequency. in the 2-channel operation mode, the samples taken from both channels are transmitted by time multiplexing in consecutive sub-frames. sub-frames related to channel 1(left or ?a? channel in stereophonic operation and primary channel in monophonic operation) normally use preamble m. however, the preamble is changed to preamble b once every 192 frame. this unit composed of 192 frames defines the block structure used to organize the channel status information. sub- frames of channel 2(right or ?b? in ster eophonic operation and secondary channel in monophonic operation) always use preamble w. in the single channel operation mode in a broadcasting studio environment the frame format is identical to the 2-channel mode. data is carried only in channel 1. in the sub-frames allocated to channel 2, time slot 28(validity flag) shall be set to logical ?1?(not valid). m channel1 w channel 2 b channel 1 w channel 2 m channel 1 w channel 2 frame 191 frame 0 frame 1 sub-frame sub-frame start of block
S5L840Fx spdif 12 sub-frame format (iec 60958) each sub-frame is divided into 32 time slot, numbered from 0 to 31. time slot 0 to 3 carry one of the three permitted preambles. these are used to affect synchronization of sub-frames, frames and blocks. time slots 4 to 27 carry the audio sample word in linear 2?s complement representation. the most significant bit is carrie d by time slot 27. when a 24-bit coding range is used, the least significant bit is in time slot 4. when a 20-bit coding range is sufficient, the least significant bit is in time slot 8 and time slot 4 to 7 may be used for other application. under these circumstances, the bits in the time slot 4 to 7 are designated auxiliary sample bits. if the source provides fewer bits than the interf ace allows(24 or 20), the unused least significant bits shall be set to a logical ?0?. by this procedure, equipment using different numbers of bits may be connected together. time slot 28 carries the validity flag associated with the audio sample word. this flag is set to logical ?0? if the audio sample is reliable. time slot 29 carries one bit of the user data associated with the audio channel transmitted in the same sub-frame. the default value of the user bit is logical ?0?. time slot 30 car ries one bit of the channel status words associated with the audio channel transmitted in the same sub-frame. time slot 31 carries a parity bit such that time slots 4 to 31 inclusive will carry an even number of ones and an even number of zeros. sync preamble aux audio sample word v u c p 0 34 78 28 31 l s b l s b m s b validity flag user data channel status parity bit channel coding to minimize the dc component on the transmission lin e, to facilitate clock recovery from the data stream and to make the interface insensitive to the polarity of connections, time slots 4 to 31 are encoded in biphase-mark. each bit to be transmitt ed is represented by a symbol comprising two consecutive binary states. the first state of a symbol is always different from the second state of the previous symbol. the second state of the symbol is identical to the first if the bit to be transmitted is logical ?0?, is different from the first if the bit is logical ?1?. clock (twice bit rate) source coding channel coding (bi-phase mark)
S5L840Fx spdif 13 preamble preambles are specific patterns providing synchron ization and identification of the sub-frames and blocks. a set of three preambles is used. these pr eambles are transmitted in the time allocated to four time slots(time slots 0 to 3) and are represent ed by eight successive states. the first state of the preamble is always different from the second state of the previous symbol. like bi-phase code, these preambles are dc free and provide clock recovery. they differ in at least two states from any valid biphase sequence. non-linear pcm encoded source(iec 61937) the non-linear pcm encoded audio bitstream is transferred using the basic 16-bit data area of the iec 60958 subframes, i.e. in time slots 12 to 27. each iec 60958 frame can transfer 32 bits of the non-pcm data in consumer application mode. when the spdif bitstream conveys linear pcm audio, the symbol frequency is 64 times the pcm sampling frequency(32 time slots per pcm sample times two channels). when a non-linear pcm encoded audio bitstream is conveyed by the interface, the symbol frequency shall be 64 times the sampling rate of the encoded audio within that bitstream. but in the case where a non-linear pcm encoded audio bitstream is conveyed by the interface containing audio with low sampling frequency, the symbol frequency shall be 128 times the sampling rate of the encoded audio within that bitstream. each data burst contains a burst-preamble consis ting of four 16-bit words (pa, pb, pc, pd), followed by the burst-payload which contains data of an encoded audio frame. the burst-preamble consists of four mandatory fields. pa and pb represent a synchronization word; pc gives information about the type of data and some information/control for the receiver; pd gives the length of the burst-payload, limited to 2 16 (=65,535) bits. the four preamble words are contained in two sequential spdif frames. the frame beginning the data-burst contains preamble word pa in subf rame 1 and pb in subframe 2. the next frame contains pc in subframe 1 and pd in subframe 2. when placed into a spdif subframe, the msb of a 16-bit burst-preamble is placed into time sl ot 27 and the lsb is placed into time slot 12. data-burst stuffing data-burst stuffing data-burst stuffing data-burst ... pa pb pa pc burst-payload pb pc pd pd repetition period between two data-bursts
S5L840Fx spdif 14 spdif operation since the bit frequency of spdif is 128fs(fs : samling frequency), the main clock of spdif is made by dividing audio main clock(mclk) depending on the frequency of mclk. mclk is divided by 2 in case of 256fs, by 3 in case of 384fs and by 4 in case of 512fs. spdif module in S5L840Fx plays the role of transforming audio sample data into the format of spdif. to do this, spdif module inserts preamble data, channel status data, user data, error check bit and parity bit into the appropriate time slots. preamble data are fixed in the module and inserted depending on subframe counter. channel status data are set in the spdcstas register and used by one bit per frame. user data always have zero values. for non-linear pcm data, burst-preamble which consists of pa, pb, pc and pd must be inserted before burst-payload and zero is stuffed from the end of burst-payload to the repetition count. pa(=16?hf872) and pb(=16?h4e1f) is fixed in the module and pc and pd is set in the register spdbstas. to stuff zero, the end of burst-payload is calculated from pd value and repetition count which depends on data type in the preamble pc is acquired from register spdcnt. audio data are justified to the lsb. 16- , 20- or 24-bit pcm data and 16-bit stream data are supported. the unoccupied upper bits of 32-bit word are ignored. data are fetched through dma request. when one of two data buffers is empty, dma service is requested. audio data stored in the data buffers are transformed into spdif format and output to the port. for non-linear pcm data, interrupt is generated after audio data are output up to the value specified in the spdcnt register. interru pt makes the registers such as spdbstas and spdcnt be set to new values when data type of new bitstream is different from the previous one.
lcd interface controller overview lcd interface controller supports the interface between lcd con troller with 6800series (motorola) and 8080serise(intel). feather z 8/4 bit parallel interface mode(6800/8080). z 3 pin / 4 pin serial interface mode. z support multiple frequencies inte rnal clock for high and low sp eed controller. z contains an 16 bytes fifo for sending control and data informat ion to the lcd controller. z apply 32 bits, 16bit and 8bit write apb bus on fifo. z contains maskable interrupts.
block diagram apb i/f & contoller clk_gen fifo p_interface s_interface out parallel i/f serial i/f lcd i/f apb bus i/f pclk lcd_clk 1. apb i/f & controller : this block supports the interface with h ost and generate the control signal, interrupt and status. 2. clk_gen : as to the value set in register, this block generate the lcd clock which is used as clock source in this block. (1/2/4/8/16/32/64/ 128 divider). 3. fifo : 9 bits x 16 depth fifo. msb 1bit is used as rs signal(c ommand/data) lsb 8 bits is used for sending data. each data is send to p_int erface or s_interface block as to control register. 4. p_interface : this block control the data transfer including co ntrol signal in parallel mode. in serial mode, this block is disabled. 5. s_interface : this block control the data transfer including co ntrol signal in serial mode. in parallel mo de, this block is disabled.
pin description width i/o description testmode 1 i for scan enable signal pclk 1 i global clock presetn 1 i global reset apb interface psel 1 i selection in apb penable 1 i enable in apb pwrite 1 i write / read in apb paddr 4 i address in apb pwdata 9 i write data in apb prdata 9 o read data in apb lcd driver interface lcd_rst 1 o lcd driver reset lcd_csb 1 o lcd driver chip select lcd_rs 1 o lcd driver register select. lcd_rw_wr 1 o read / write execution control pin lcd_e_rd 1 o read / write execution control pin lcd_db[3:0] 4 i/o bi-directional data bus(8bit mode) lcd_db[5:4] 2 i/) bi-direction al data bus(8bit/4bit mode) lcd_db[6]/sclk 1 i/o bi-directional data bus & sclk lcd_db[7]/sdo 1 i/o bi-directional data bus & sdo interrupt interface int_lcd 1 o interrupt signal
lcd driver interface z lcd_rst : lcd driver reset signal. z lcd_csb : lcd driver chip select signal. z lcd_rs : lcd driver re gister select signal. rs = 1 : db0 to db7 are display data. rs = 0 : db0 to db7 are control data. z lcd_rw_wr : read / write execution control pin. in 6800 mode, high : read, low : write. in 8080 mode, write enable sognal. z lcd_e_rd : read / write execution control pin. in 6800 mode, read / write enable signal. in 8080 mode, read enable signal. z db[3:0] : bi-directional data bus low 4bits. z db[5:4] : bi-directional data bus data[5:4] bit & data[1:0] bit at 4bit mode. z db[6] : bi-directional data bus data[6], data[2] at parallel mo de, serial clock(sclk) at serial mode. z db[7] : bi-directional data bus data[7], data[3] at parallel mo de, serial output data(sdo) at serial mode.
timing diagram rs rw csb db_w db_r 6800 mode e rs /rd /wr csb db_w db_r 8080 mode sclk csb rs sdo serial mode
registers name width address r/w description rest value lcd_con 32 0xhhhh 0000 r/w control register. 0x0000 0000 lcd_wcmd 32 0xhhhh 0004 w write command register. 0x0000 0000 lcd_wdata 32 0xhhhh 0008 w writ e data register 0x0000 0000 lcd_rcmd 32 0xhhhh 000c w read command register. 0x0000 0000 lcd_rdata 32 0xhhhh 0010 w read data register. 0x0000 0000 lcd_dbuff 32 0xhhhh 0014 r read data buffer 0x0000 0000 lcd_intcon 32 0xhhhh 0018 r/w inte rrupt control register 0x0000 0 000 lcd_status 32 0xhhhh 001c r lc d interface status 0x0000 0000 lcd_phtime 32 0xhhhh 0020 r/w pha se time register 0x0000 0066 lcd_con 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description reset value 9 lcd_on r/w lcd interface on. 0 8:7 w_len r/w apb bus interface word length. 00 : 8 bit. 01 : 16 bit 10 : 32 bit 00 6 endian r/w apb bus word endian. 0 : little endian. 1 : big endian. when w_len = 0, no effect. 0 5 ps1 r/w microprocessor interface select. when ps0 = 0 ps1 = 0 : 3 pin-spi mpu interface. ps1 = 1 : 4 pin-spi mpu interface. when ps0 = 1 0
ps1 = 0 : 8080-series parallel mpu interface. ps2 = 1 : 6800-series parallel mpu interface. 4 ps0 r/w parallel/s erial data select. when 0 serial mpu interface. when 1 parallel mpu interface. 0 3 bus_m r/w bus mode select at parallel interface. bus_m = 0 : 8bit data bus. bus_m = 1 : 4 bit data bus. 0 2:0 clk_sel r/w lcd clock select. 000 : pclk / 1, 001 : pclk / 2 010 : pclk / 4, 011 : pclk / 8 100 : pclk / 16, 101 : pclk / 32 110 : pclk / 64, 111 : pclk / 128 0 lcd_wcmd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description rest value 7:0 wcmd w write lcd driver command. 0x000 lcd_wdata 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bit name type description rest value 31:0 * wdata w write lcd driver data. 0x000 z note : in 8bit length mode, 31~ 8 data bits are not valid. lcd_rcmd 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description rest value 7:0 rcmd w read command lcd driver command. ] dummy value. 0x000 lcd_rdata 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description rest value 7:0 rdata w read command lcd driver data. dummy value. 0x000 lcd_dbuff 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
bit name type description rest value 7:0 dbuff w read lcd driver data buff. 0x000 lcd_status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description rest value 7 interrupt r interrupt flag. 0 6 reserved r 0 5 ow r fifo is over write. 0 4 full r fifo is full. 0 3 hfull r fifo is half full. 0 2 hempty r fifo is half empty. 1 empty r fifo is empty. 0 0 readon r read operation done. 1 lcd_int_con 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description rest value 7 int_en r/w interrupt enable. 0 6 f_clear r/w fifo clear. 0 5 ow_en r/w over write interrupt enable. 0 4 f_en r/w fifo full i nterrupt enable. 0
3 hf_en r/w fifo half full interrupt enable. 0 2 he_en r/w fifo half empty interrupt enable. 0 1 em_en r/w fifo empty interrupt enable. 0 0 red_en r/w read done interrupt enable. 0 lcd_phtime 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name type description rest value 7:4 ph1_time r/w phase 1 time register 6 3:0 ph2_time r/w phase 1 time register 0
operation - clock select as to the operation frequency of lcd driver ic, cpu selects the frequency of clock in lcd interface controller. there is the register for this operat ion. using this internal clock, the following signals, rd_rw, e_rd and csb are generated . at this time, the high pulse width(tpwh ) and the low pulse width (tpwl) is controlled also by lcd_phtime registe. pclk clk_sel tpw time unit (ns) 000 ( x 1 ) 10 001 ( x 1/2) 20 010 ( x 1/4) 40 011 ( x 1/8) 80 100 ( x 1/16) 160 101 ( x 1/32) 320 110 (x 1/64) 640 100 mhz 111 ( x 1/128) 1280 000 ( x 1 ) 20 001 ( x 1/2) 40 -- -- 110 ( x 1/64) 1280 50 mhz 111 ( x 1/128) 2560 tpw = (ph1_time value + 1) x tpw time unit (phase 1) tpw = (ph2_time value + 1) x tpw time unit (phase 2) - mode select the bit ps1 and ps0 of control r egister set the interface mode. ps0 ps1 interface mode data /instruction data read/write serial clock 0 0 serial (3 pin) none sdo(db7) write only sclk(db6) 0 1 serial (4 pin) rs sdo(db7) write only sclk(db6)
1 0 parallel (8080) rs db[7:0] read : e_rd write : rw_wr none 1 1 parallel (6800) rs db[7:0] read : rw_wr = high write : rw_wr = low none in parallel interface mode, using the bus_m bit of control regi ster, 8bit data bus mode or 4bit data bus mode is set. - interrupt control there are 5 interrupt sou rces as the following: 1) read done 2) fifo empty 3) fifo half empty 4) fifo full 5) fifo over run each interrupt source can be mask ed each maskable control bit o r common interrupt mask bit. if the interrupt is occurred at once, cpu can find ou t the source by reading status register. the way of clearing each inte rrupt source is as following: 1) fifo empty or fifo half empty: writing the data to fifo. 2) fifo full or fifo over run: clearing fifo 3) read done : reading lcd_dbuff register. - lcd command & data the bit position 7 in fifo named rs bit is used as indiacating the data or command. this value is set automatically as to writing to which register . to write command to lcd driver, cpu have to write to lcd_wcmd. at this time, the value of rs is set automatically as zero. lcd interfase control ler outputs the command to lcd driver ic. to write data to lcd driver, cpu has to write to lcd_wdata. at this time, the value of rs is set automatically as one. lcd interface controller out puts the data to lcd driver ic. to read the status of lcd driver, cpu writes the dummy data to lcd_rcmd register.
then, the status value is saved in lcd_dbuff. to read the data of lc d driver, cpu writes the dummy data to lc d_rdat register. then, the status value is saved in lcd_dbuff. after reading the status or data is finished, the read_done_fla g is set to high. cpu read this value usin g interrupt or polling.

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